Delay-locked loop circuit controlled by column strobe write latency
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United States of America Patent
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Nov 1, 2011
Grant Date -
Jun 24, 2010
app pub date -
Dec 22, 2009
filing date -
Dec 22, 2008
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The DLL circuit includes a control circuit which controls bias currents of the unit delay circuits according to an externally input column address strobe writing latency (CWL) signal, and/or a DCC control circuit which adjusts steps of a DCC current of the DCC according to the externally input column address strobe writing latency (CWL) signal. The CWL signal may be input by a semiconductor memory device and may be indicative of a column address strobe writing latency of the semiconductor memory device. The semiconductor memory device may be a double data rate (DDR) synchronous DRAM (SDRAM) device.
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