Alternate 4-terminal JFET geometry to reduce gate to source capacitance
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United States of America Patent
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Nov 15, 2011
Grant Date -
Apr 7, 2011
app pub date -
Oct 7, 2009
filing date -
Oct 7, 2009
priority date (Note) -
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Abstract
A 4-Terminal JFET includes a substrate having a first conduction type and an upper layer having a second, opposite, conduction type over the substrate. A gate and a source are embedded in the upper layer. A gate pad is electrically connected to the gate. A region, which has a first conduction type, is formed in the upper layer and separates the upper layer into two sections. This region reduces the overall capacitance between the gate pad and the source. Reduced overall gate to source capacitance can result in reduced noise amplification in the JFET.
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