2T2R-1T1R mix mode phase change memory array
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United States of America Patent
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Nov 22, 2011
Grant Date -
Mar 17, 2011
app pub date -
Sep 17, 2009
filing date -
Sep 17, 2009
priority date (Note) -
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Abstract
A memory device as described herein includes an array of programmable resistance memory cells. The memory device further includes sense circuitry having a dual memory cell (2T-2R) mode to read a data value stored in a pair of memory cells in the array based on a difference in resistance between a first memory cell in the pair and a second memory cell in the pair. The sense circuitry also has a single memory cell (1T-1R) mode to read a data value in a particular memory cell in the array based on the resistance of the particular memory cell.
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