Microelectronic assemblies having very fine pitch stacking
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United States of America Patent
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Nov 29, 2011
Grant Date -
Jun 28, 2007
app pub date -
Dec 23, 2005
filing date -
Dec 23, 2005
priority date (Note) -
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Abstract
A method of making a stacked microelectronic assembly includes providing a first microelectronic package that includes a first substrate having a first dielectric layer, conductive posts, and conductive traces extending along the surface of the first dielectric layer; providing a second microelectronic package including a second substrate that includes a second dielectric layer; securing a microelectronic element to one of the surfaces of at least one of the first or second substrates; and joining the conductive posts of the first substrate with the fusible masses of the second substrate. The posts may include a plurality of aligned posts which are aligned in a first row extending in a single orthogonal direction along a surface of the first substrate away from a portion of the first substrate that faces a face of the microelectronic element. The aligned posts are disposed beyond one of the edges of the microelectronic element.
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