Ferroelectric memory with sub bit-lines connected to each other and to fixed potentials
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United States of America Patent
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Dec 13, 2011
Grant Date -
Sep 17, 2009
app pub date -
May 22, 2009
filing date -
Apr 26, 2006
priority date (Note) -
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Abstract
A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.
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