US Patent No: 8,077,535

Number of patents in Portfolio can not be more than 2000

Memory refresh apparatus and method

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ALSO PUBLISHED AS: 20080025122
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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A system and method are provided. The system and method simulate a DRAM memory circuit using an interface circuit connected to a plurality of other DRAM memory circuits. In response to the receipt of a refresh control signal, a first refresh control signal is sent to a first subset of the plurality of other DRAM memory circuits and a second refresh control signal is sent to a second subset of the plurality of other DRAM memory circuits.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
GOOGLE INC.MOUNTAIN VIEW, CA8952

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rajan, Suresh Natarajan San Jose, CA 111 2487
Schakel, Keith R San Jose, CA 92 2359
Smith, Michael John Sebastian Palo Alto, CA 97 2344
Wang, David T San Jose, CA 128 2638
Weber, Frederick Daniel San Jose, CA 80 2161

Cited Art Landscape

Patent Info (Count) # Cites Year
 
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5,729,503 Address transition detection on a synchronous design 85 1995
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5,668,773 Synchronous burst extended data out DRAM 83 1995
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5,721,859 Counter control circuit in a burst memory 81 1995
5,604,714 DRAM having multiple column address strobe operation 62 1995
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GOOGLE INC. (62)
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2008/0028,135 MULTIPLE-COMPONENT MEMORY INTERFACE SYSTEM AND METHOD 49 2006
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2008/0037,353 Interface circuit system and method for performing power saving operations during a command-related latency 42 2006
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2008/0123,459 COMBINED SIGNAL DELAY AND POWER SAVING SYSTEM AND METHOD FOR USE WITH A PLURALITY OF MEMORY CIRCUITS 44 2006
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2008/0056,014 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 47 2007
2008/0062,773 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 47 2007
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2008/0028,136 METHOD AND APPARATUS FOR REFRESH MANAGEMENT OF MEMORY MODULES 43 2007
2008/0028,137 Method and Apparatus For Refresh Management of Memory Modules 48 2007
2008/0103,753 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 50 2007
2008/0104,314 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 47 2007
2008/0109,206 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 47 2007
2008/0109,595 SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS 51 2007
2008/0109,597 METHOD AND APPARATUS FOR REFRESH MANAGEMENT OF MEMORY MODULES 47 2007
2008/0109,598 Method and apparatus for refresh management of memory modules 48 2007
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2008/0126,687 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 47 2007
2008/0126,688 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 47 2007
2008/0126,689 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 47 2007
2008/0126,692 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 47 2007
2008/0133,825 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 47 2007
2009/0024,789 MEMORY CIRCUIT SYSTEM AND METHOD 59 2007
2009/0024,790 MEMORY CIRCUIT SYSTEM AND METHOD 47 2007
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2009/0216,939 Emulation of abstracted DIMMs using abstracted DRAMs 43 2009
2009/0285,031 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 44 2009
2009/0290,442 METHOD AND CIRCUIT FOR CONFIGURING MEMORY CORE INTEGRATED CIRCUIT DIES WITH MEMORY INTERFACE INTEGRATED CIRCUIT DIES 43 2009
2010/0020,585 METHODS AND APPARATUS OF STACKING DRAMS 44 2009
 
INTEL CORPORATION (44)
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Other [Check patent profile for assignment information] (5)
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RAMBUS INC. (1)
8,537,601 Memory controller with selective data transmission delay 0 2012

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