US Patent No: 8,077,535 - Analytics, PDF, Full Text and PAIR Access

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Memory refresh apparatus and method

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Abstract

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A system and method are provided. The system and method simulate a DRAM memory circuit using an interface circuit connected to a plurality of other DRAM memory circuits. In response to the receipt of a refresh control signal, a first refresh control signal is sent to a first subset of the plurality of other DRAM memory circuits and a second refresh control signal is sent to a second subset of the plurality of other DRAM memory circuits.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
GOOGLE INC.MOUNTAIN VIEW, CA15350

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rajan, Suresh Natarajan San Jose, US 79 4561
Schakel, Keith R San Jose, US 63 4103
Smith, Michael John Sebastian Palo Alto, US 75 4307
Wang, David T San Jose, US 92 4733
Weber, Frederick Daniel San Jose, US 54 3821

Cited Art Landscape

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2006/0117,152 Transparent four rank memory module for standard two rank sub-systems 94 2004
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (25)
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4,884,237 Stacked double density memory module using industry standard memory chips 182 1989
4,922,451 Memory re-mapping in a microcomputer system 72 1989
5,502,667 Integrated multichip memory module structure 175 1993
5,561,622 Integrated memory cube structure 172 1993
5,530,836 Method and apparatus for multiple memory bank selection 71 1994
5,513,135 Synchronous memory packaged in single/dual in-line memory module and method of fabrication 359 1994
5,563,086 Integrated memory cube, structure and fabrication 123 1995
5,872,907 Fault tolerant design for identification of AC defects including variance of cycle time to maintain system operation 82 1995
5,590,071 Method and apparatus for emulating a high capacity DRAM 93 1995
5,680,342 Memory module package with address bus buffering 70 1996
5,692,121 Recovery unit for mirrored processors 90 1996
5,802,395 High density memory modules with improved data bus performance 137 1996
5,702,984 Integrated mulitchip memory module, structure and fabrication 122 1996
5,870,350 High performance, high bandwidth memory bus architecture utilizing SDRAMs 200 1997
5,963,464 Stackable memory card 134 1998
6,070,217 High density memory module with in-line bus switches being enabled in response to read/write selection state of connected RAM banks to improve data bus performance 111 1998
6,327,664 Power management on a memory card having a signal processing element 72 1999
6,453,434 Dynamically-tunable memory controller 70 2001
6,490,161 Peripheral land grid array package with improved thermal performance 108 2002
6,968,416 Method, system, and program for processing transaction requests during a pendency of a delayed read request in a system including a bus, a target device and devices capable of accessing the target device over the bus 67 2002
7,224,595 276-Pin buffered memory module with enhanced fault tolerance 130 2004
7,539,800 System, method and storage medium for providing segment level sparing 68 2004
7,366,947 High reliability memory module with a fault tolerant address and command bus 65 2006
2008/0098,277 HIGH DENSITY HIGH RELIABILITY MEMORY MODULE WITH POWER GATING AND A FAULT TOLERANT ADDRESS AND COMMAND BUS 112 2006
 
ADVANCED MICRO DEVICES, INC. (1)
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2002/0034,068 Stacked printed circuit board memory module and method of augmenting memory therein 74 2001
 
Netlist, Inc. (11)
6,751,113 Arrangement of integrated circuits in a memory module 184 2002
6,930,900 Arrangement of integrated circuits in a memory module 76 2004
6,930,903 Arrangement of integrated circuits in a memory module 78 2004
2005/0018,495 ARRANGEMENT OF INTEGRATED CIRCUITS IN A MEMORY MODULE 122 2004
6,873,534 Arrangement of integrated circuits in a memory module 106 2004
7,286,436 High-density memory module utilizing low-density memory components 99 2005
7,254,036 High density memory module using stacked printed circuit boards 88 2005
7,289,386 Memory module decoder 110 2005
7,532,537 Memory module with a circuit providing load isolation and memory domain translation 116 2006
2006/0262,586 Memory module with a circuit providing load isolation and memory domain translation 83 2006
7,619,912 Memory module decoder 102 2007
 
AT&T IPM CORP. (1)
5,513,339 Concurrent fault simulation of circuits with both logic elements and functional circuits 150 1994
 
LSI LOGIC CORPORATION (1)
5,640,337 Method and apparatus for interim in-situ testing of an electronic system with an inchoate ASIC 82 1996
 
CISCO TECHNOLOGY, INC. (1)
7,606,245 Distributed packet processing architecture for network access servers 76 2005
 
FUJITSU LIMITED (3)
4,392,212 Semiconductor memory device with decoder for chip selection/write in 88 1980
6,664,625 Mounting structure of a semiconductor device 61 2002
7,085,941 Clock control apparatus and method, for a memory controller, that processes a block access into single continuous macro access while minimizing power consumption 70 2003
 
GODO KAISHA IP BRIDGE 1 (1)
5,973,392 Stacked carrier three-dimensional memory module and semiconductor device using the same 98 1998
 
INFINEON TECHNOLOGIES AG (7)
7,228,264 Program-controlled unit 62 2002
7,200,021 Stacked DRAM memory chip for a dual inline memory module (DIMM) 130 2004
7,266,639 Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM) 88 2004
2006/0129,712 Buffer chip for a multi-rank dual inline memory module (DIMM) 70 2004
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7,079,441 Methods and apparatus for implementing a power down in a memory device 69 2005
2006/0294,295 DRAM chip device well-communicated with flash memory chip and multi-chip package comprising such a device 114 2005
 
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5,257,233 Low power memory module using restricted RAM activation 81 1990
5,278,796 Temperature-dependent DRAM refresh circuit 182 1991
5,282,177 Multiple register block write method and circuit for video DRAMs 100 1992
5,526,320 Burst EDO memory device 173 1994
5,610,864 Burst EDO memory device with maximized write cycle timing 118 1995
5,652,724 Burst EDO memory device having pipelined output buffer 116 1995
5,675,549 Burst EDO memory device address counter 106 1995
5,598,376 Distributed write data drivers for burst access memories 142 1995
5,729,503 Address transition detection on a synchronous design 100 1995
5,724,288 Data communication for memory 66 1995
5,668,773 Synchronous burst extended data out DRAM 99 1995
5,682,354 CAS recognition in burst extended data out DRAM 89 1995
5,721,859 Counter control circuit in a burst memory 97 1995
5,604,714 DRAM having multiple column address strobe operation 77 1995
5,640,364 Self-enabling pulse trapping circuit 104 1995
5,729,504 Continuous burst edo memory device 99 1995
5,627,791 Multiple bank memory with auto refresh to specified bank 223 1996
5,661,695 Burst EDO memory device 89 1996
5,802,010 Burst EDO memory device 79 1996
5,917,758 Adjustable output driver circuit 111 1996
5,703,813 DRAM having multiple column address strobe operation 73 1996
5,696,732 Burst EDO memory device 81 1996
5,706,247 Self-enabling pulse-trapping circuit 92 1996
5,949,254 Adjustable output driver circuit 143 1996
5,923,611 Memory having a plurality of external clock signal inputs 82 1996
5,838,177 Adjustable output driver circuit having parallel pull-up and pull-down elements 173 1997
5,757,703 Distributed write data drivers for burst access memories 87 1997
5,717,654 Burst EDO memory device with maximized write cycle timing 91 1997
5,812,488 Synchronous burst extended data out dram 81 1997
5,870,347 Multi-bank memory input/output line selection 125 1997
5,875,142 Integrated circuit with temperature detector 114 1997
5,831,931 Address strobe recognition in a memory device 69 1997
5,946,265 Continuous burst EDO memory device 94 1997
5,831,932 Self-enabling pulse-trapping circuit 73 1997
5,850,368 Burst EDO memory address counter 84 1997
6,002,613 Data communication for memory 66 1997
5,963,504 Address transition detection in a synchronous design 89 1997
6,016,282 Clock vernier adjustment 283 1998
6,069,504 Adjustable output driver circuit having parallel pull-up and pull-down elements 97 1998
6,029,250 Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same 397 1998
6,101,612 Apparatus for aligning clock and data signals received from a RAM 107 1998
6,108,795 Method for aligning clock and data signals received from a RAM 103 1998
6,044,032 Addressing scheme for a double data rate SDRAM 110 1998
6,002,627 Integrated circuit with temperature detector 100 1999
6,026,050 Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same 195 1999
6,326,810 Adjustable output driver circuit 75 1999
6,084,434 Adjustable output driver circuit 79 1999
6,453,402 Method for synchronizing strobe and data signals from a RAM 84 1999
6,307,769 Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices 85 1999
6,260,154 Apparatus for aligning clock and data signals received from a RAM 70 2000
6,330,683 Method for aligning clock and data signals received from a RAM 84 2000
6,356,500 Reduced power DRAM device and method 107 2000
6,496,440 Method and system for accessing rows in multiple memory banks within an integrated circuit 77 2001
6,801,989 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same 84 2001
6,437,600 Adjustable output driver circuit 74 2001
6,754,129 Memory module with integrated bus termination 69 2002
7,149,824 Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction 66 2002
7,120,727 Reconfigurable memory module and method 159 2003
7,428,644 System and method for selective memory module power management 80 2003
7,210,059 System and method for on-board diagnostics of memory modules 100 2003
6,862,202 Low power memory module using restricted device activation 58 2003
2006/0041,730 Memory command delay balancing in a daisy-chained memory topology 88 2004
7,046,538 Memory stacking system and method 82 2004
7,245,541 Active termination control 67 2005
7,269,042 Memory stacking system and method 87 2006
7,437,579 System and method for selective memory module power management 70 2006
 
EMC CORPORATION (3)
5,798,961 Non-volatile memory module 104 1994
5,742,792 Remote data mirroring 728 1996
6,058,451 Method and apparatus for refreshing a non-clocked memory 70 1997
 
INTEL CORPORATION (42)
5,388,265 Method and apparatus for placing an integrated circuit chip in a reduced power consumption state 190 1993
5,860,106 Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem 181 1995
5,692,202 System, apparatus, and method for managing power in a computer system 100 1995
6,279,069 Interface for flash EEPROM memory arrays 324 1996
5,884,088 System, apparatus and method for managing power in a computer system 101 1997
5,835,435 Method and apparatus for dynamically placing portions of a memory in a reduced power consumtion state 116 1997
6,298,426 Controller configurable for use with multiple memory organizations 113 1997
6,968,419 Memory module having a memory module controller controlling memory transactions for a plurality of memory devices 106 1998
6,970,968 Memory module controller for providing an interface between a system memory controller and a plurality of memory devices on a memory module 154 1998
6,233,650 Using FET switches for large memory arrays 147 1998
6,199,151 Apparatus and method for storing a device row indicator for use in a subsequent page-miss memory cycle 61 1998
6,587,912 Method and apparatus for implementing multiple memory buses on a memory module 302 1998
6,038,673 Computer system with power management scheme for DRAM devices 81 1998
6,442,698 Method and apparatus for power management in a memory subsystem 93 1998
6,457,095 Method and apparatus for synchronizing dynamic random access memory exiting from a low power state 76 1999
6,564,285 Synchronous interface for a nonvolatile memory 197 2000
6,356,105 Impedance control system for a center tapped termination bus 124 2000
6,317,352 Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules 329 2000
6,487,102 Memory module having buffer for isolating stacked memory devices 185 2000
* 6,553,450 Buffer to multiply memory interface 184 2000
6,820,163 Buffering data transfer between a chipset and memory modules 85 2000
6,862,653 System and method for controlling data flow direction in a memory system 64 2000
6,618,791 System and method for controlling power states of a memory device via detection of a chip select signal 99 2000
6,785,767 Hybrid mass storage system and method with two different types of storage medium 120 2000
6,563,337 Driver impedance control mechanism 75 2001
6,820,169 Memory control with lookahead power management 76 2001
2003/0105,932 Emulation of memory clock enable pin and use of chip select for memory power control 71 2001
6,714,891 Method and apparatus for thermal management of a power supply to a high performance processor in a computer system 95 2001
6,799,241 Method for dynamically adjusting a memory page closing policy 109 2002
7,024,518 Dual-port buffer-to-memory interface 93 2002
6,795,899 Memory system with burst length shorter than prefetch length 198 2002
7,103,730 Method, system, and apparatus for reducing power consumption of a memory 86 2002
6,639,820 Memory buffer arrangement 79 2002
6,747,887 Memory module having buffer for isolating stacked memory devices 83 2002
2005/0108,460 Partial bank DRAM refresh 75 2003
7,127,567 Performing memory RAS operations over a point-to-point interconnect 66 2003
2005/0138,267 Integral memory buffer and serial presence detect capability for fully-buffered memory modules 181 2003
7,085,152 Memory system segmented power supply and control 70 2003
7,133,960 Logical to physical address mapping of chip selects 100 2003
2005/0195,629 Interchangeable connection arrays for double-sided memory module placement 67 2004
2005/0204,111 Command scheduling for dual-data-rate two (DDR2) memory devices 64 2004
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5,104,820 Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting 266 1991
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6,665,227 Method and apparatus for reducing average power in RAMs by dynamically changing the bias on PFETs contained in memory cells 66 2001
7,028,215 Hot mirroring in a computer system with redundant memory subsystems 66 2002
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2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
 
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6,338,108 Coprocessor-integrated packet-type memory LSI, packet-type memory/coprocessor bus, and control method thereof 86 1998
 
AMIGA DEVELOPMENT LLC, A LIMITED LIABILITY COMPANY OF THE STATE OF DELAWARE (1)
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2006/0248,387 In-line non volatile memory disk read cache and write buffer 176 2005
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6,779,097 High bandwidth memory interface 72 2002
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6,992,950 Delay locked loop implementation in a synchronous dynamic random access memory 65 2003
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2008/0065,820 High bandwidth memory interface 64 2007
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UNISYS CORPORATION (2)
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6,674,154 Lead frame with multiple rows of external terminals 65 2002
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* Cited By Examiner

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
PATENTS1, LLC (1)
9,164,679 System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class 0 2015
 
INPHI CORPORATION (1)
9,123,441 Backward compatible dynamic random access memory device and method of testing therefor 0 2014
 
RAMBUS INC. (2)
* 8,537,601 Memory controller with selective data transmission delay 3 2012
* 2012/0287,725 MEMORY CONTROLLER WITH SELECTIVE DATA TRANSMISSION DELAY 1 2012
 
P4TENTS1, LLC (8)
8,930,647 Multiple class memory systems 13 2012
9,223,507 System, method and computer program product for fetching data between an execution of a plurality of threads 0 2015
9,195,395 Flash/DRAM/embedded DRAM-equipped system and method 0 2015
9,189,442 Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system 0 2015
9,182,914 System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class 0 2015
9,176,671 Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system 0 2015
9,170,744 Computer program product for controlling a flash/DRAM/embedded DRAM-equipped system 0 2015
9,158,546 Computer program product for fetching from a first physical memory between an execution of a plurality of threads associated with a second physical memory 0 2015
* Cited By Examiner

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