US Patent No: 8,077,535 - Analytics, PDF, Full Text and PAIR Access

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Memory refresh apparatus and method

ALSO PUBLISHED AS: 20080025122

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Abstract

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A system and method are provided. The system and method simulate a DRAM memory circuit using an interface circuit connected to a plurality of other DRAM memory circuits. In response to the receipt of a refresh control signal, a first refresh control signal is sent to a first subset of the plurality of other DRAM memory circuits and a second refresh control signal is sent to a second subset of the plurality of other DRAM memory circuits.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
GOOGLE INC.MOUNTAIN VIEW, CA10880

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rajan, Suresh Natarajan San Jose, CA 120 3173
Schakel, Keith R San Jose, CA 97 2970
Smith, Michael John Sebastian Palo Alto, CA 103 2946
Wang, David T San Jose, CA 139 3337
Weber, Frederick Daniel San Jose, CA 85 2736

Cited Art Landscape

Patent Info (Count) # Cites Year
 
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5,278,796 Temperature-dependent DRAM refresh circuit 167 1991
5,282,177 Multiple register block write method and circuit for video DRAMs 94 1992
5,526,320 Burst EDO memory device 167 1994
5,610,864 Burst EDO memory device with maximized write cycle timing 113 1995
5,652,724 Burst EDO memory device having pipelined output buffer 111 1995
5,675,549 Burst EDO memory device address counter 101 1995
5,598,376 Distributed write data drivers for burst access memories 136 1995
5,729,503 Address transition detection on a synchronous design 96 1995
5,724,288 Data communication for memory 62 1995
5,668,773 Synchronous burst extended data out DRAM 94 1995
5,682,354 CAS recognition in burst extended data out DRAM 85 1995
5,721,859 Counter control circuit in a burst memory 92 1995
5,604,714 DRAM having multiple column address strobe operation 73 1995
5,640,364 Self-enabling pulse trapping circuit 99 1995
5,729,504 Continuous burst edo memory device 94 1995
5,627,791 Multiple bank memory with auto refresh to specified bank 215 1996
5,661,695 Burst EDO memory device 84 1996
5,802,010 Burst EDO memory device 75 1996
5,917,758 Adjustable output driver circuit 105 1996
5,703,813 DRAM having multiple column address strobe operation 69 1996
5,696,732 Burst EDO memory device 77 1996
5,706,247 Self-enabling pulse-trapping circuit 85 1996
5,949,254 Adjustable output driver circuit 129 1996
5,923,611 Memory having a plurality of external clock signal inputs 78 1996
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5,870,347 Multi-bank memory input/output line selection 111 1997
5,875,142 Integrated circuit with temperature detector 104 1997
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5,946,265 Continuous burst EDO memory device 90 1997
5,831,932 Self-enabling pulse-trapping circuit 69 1997
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5,963,504 Address transition detection in a synchronous design 85 1997
6,016,282 Clock vernier adjustment 260 1998
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7,120,727 Reconfigurable memory module and method 146 2003
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GOOGLE INC. (62)
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2008/0025,108 SYSTEM AND METHOD FOR DELAYING A SIGNAL COMMUNICATED FROM A SYSTEM TO AT LEAST ONE OF A PLURALITY OF MEMORY CIRCUITS 59 2006
2008/0025,122 MEMORY REFRESH SYSTEM AND METHOD 56 2006
2008/0025,136 SYSTEM AND METHOD FOR STORING AT LEAST A PORTION OF INFORMATION RECEIVED IN ASSOCIATION WITH A FIRST OPERATION FOR USE IN PERFORMING A SECOND OPERATION 59 2006
2008/0025,137 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 63 2006
2008/0027,702 SYSTEM AND METHOD FOR SIMULATING A DIFFERENT NUMBER OF MEMORY CIRCUITS 59 2006
2008/0028,135 MULTIPLE-COMPONENT MEMORY INTERFACE SYSTEM AND METHOD 63 2006
2008/0031,072 POWER SAVING SYSTEM AND METHOD FOR USE WITH A PLURALITY OF MEMORY CIRCUITS 54 2006
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2007/0058,471 Methods and apparatus of stacking DRAMs 71 2006
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7,392,338 Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits 58 2006
7,472,220 Interface circuit system and method for performing power management operations utilizing power management signals 59 2006
7,590,796 System and method for power management in memory systems 59 2006
2008/0031,030 System and method for power management in memory systems 75 2006
2008/0082,763 APPARATUS AND METHOD FOR POWER MANAGEMENT OF MEMORY CIRCUITS BY A SYSTEM OR COMPONENT THEREOF 58 2006
7,581,127 Interface circuit system and method for performing power saving operations during a command-related latency 56 2006
2008/0037,353 Interface circuit system and method for performing power saving operations during a command-related latency 54 2006
2008/0027,697 MEMORY CIRCUIT SIMULATION SYSTEM AND METHOD WITH POWER SAVING CAPABILITIES 56 2006
2008/0027,703 MEMORY CIRCUIT SIMULATION SYSTEM AND METHOD WITH REFRESH CAPABILITIES 55 2006
2008/0123,459 COMBINED SIGNAL DELAY AND POWER SAVING SYSTEM AND METHOD FOR USE WITH A PLURALITY OF MEMORY CIRCUITS 56 2006
2008/0086,588 System and Method for Increasing Capacity, Performance, and Flexibility of Flash Storage 65 2006
2007/0195,613 Memory module with memory stack and interface with enhanced capabilities 78 2007
2008/0126,690 Memory module with memory stack 80 2007
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2007/0204,075 SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS 66 2007
2008/0056,014 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 60 2007
2008/0062,773 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 59 2007
2008/0010,435 MEMORY SYSTEMS AND MEMORY MODULES 83 2007
2008/0028,136 METHOD AND APPARATUS FOR REFRESH MANAGEMENT OF MEMORY MODULES 56 2007
2008/0028,137 Method and Apparatus For Refresh Management of Memory Modules 61 2007
2008/0103,753 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 64 2007
2008/0104,314 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 60 2007
2008/0109,206 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 60 2007
2008/0109,595 SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS 64 2007
2008/0109,597 METHOD AND APPARATUS FOR REFRESH MANAGEMENT OF MEMORY MODULES 60 2007
2008/0109,598 Method and apparatus for refresh management of memory modules 61 2007
2008/0120,443 SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS 62 2007
2008/0126,687 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 60 2007
2008/0126,688 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 60 2007
2008/0126,689 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 60 2007
2008/0126,692 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 61 2007
2008/0133,825 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 60 2007
2009/0024,789 MEMORY CIRCUIT SYSTEM AND METHOD 72 2007
2009/0024,790 MEMORY CIRCUIT SYSTEM AND METHOD 61 2007
2008/0115,006 SYSTEM AND METHOD FOR ADJUSTING THE TIMING OF SIGNALS ASSOCIATED WITH A MEMORY SYSTEM 71 2007
7,599,205 Methods and apparatus of stacking DRAMs 64 2008
2008/0170,425 METHODS AND APPARATUS OF STACKING DRAMS 79 2008
7,730,338 Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits 57 2008
7,761,724 Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit 55 2008
2008/0239,857 INTERFACE CIRCUIT SYSTEM AND METHOD FOR PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH ONLY A PORTION OF A MEMORY CIRCUIT 55 2008
2008/0239,858 INTERFACE CIRCUIT SYSTEM AND METHOD FOR AUTONOMOUSLY PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH A PLURALITY OF MEMORY CIRCUITS 55 2008
2009/0216,939 Emulation of abstracted DIMMs using abstracted DRAMs 56 2009
2009/0285,031 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 56 2009
2009/0290,442 METHOD AND CIRCUIT FOR CONFIGURING MEMORY CORE INTEGRATED CIRCUIT DIES WITH MEMORY INTERFACE INTEGRATED CIRCUIT DIES 56 2009
2010/0020,585 METHODS AND APPARATUS OF STACKING DRAMS 56 2009
 
INTEL CORPORATION (44)
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5,692,202 System, apparatus, and method for managing power in a computer system 92 1995
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2003/0105,932 Emulation of memory clock enable pin and use of chip select for memory power control 66 2001
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6,799,241 Method for dynamically adjusting a memory page closing policy 97 2002
7,024,518 Dual-port buffer-to-memory interface 83 2002
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7,103,730 Method, system, and apparatus for reducing power consumption of a memory 80 2002
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6,839,290 Method, apparatus, and system for high speed data transfer using source synchronous data strobe 61 2003
2005/0108,460 Partial bank DRAM refresh 68 2003
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RAMBUS INC. (44)
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6,378,020 System having double data transfer rate and intergrated circuit therefor 69 2000
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6,701,446 Power control system for synchronous memory device 102 2001
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6,597,616 DRAM core refresh with reduced spike current 57 2002
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6,560,158 Power down voltage control method and apparatus 71 2001
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RENESAS ELECTRONICS CORPORATION (13)
5,220,672 Low power consuming digital circuit device 95 1991
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TDK CORPORATION (13)
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
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2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
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QIMONDA AG (12)
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6,986,118 Method for controlling semiconductor chips and control apparatus 62 2003
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CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. (11)
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Netlist, Inc. (11)
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Other [Check patent profile for assignment information] (5)
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RAMBUS INC. (1)
8,537,601 Memory controller with selective data transmission delay 0 2012

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