US Patent No: 8,077,535 - Analytics, PDF, Full Text and PAIR Access

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Memory refresh apparatus and method

ALSO PUBLISHED AS: 20080025122

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Abstract

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A system and method are provided. The system and method simulate a DRAM memory circuit using an interface circuit connected to a plurality of other DRAM memory circuits. In response to the receipt of a refresh control signal, a first refresh control signal is sent to a first subset of the plurality of other DRAM memory circuits and a second refresh control signal is sent to a second subset of the plurality of other DRAM memory circuits.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
GOOGLE INC.MOUNTAIN VIEW, CA12787

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rajan, Suresh Natarajan San Jose, CA 123 3535
Schakel, Keith R San Jose, CA 99 3283
Smith, Michael John Sebastian Palo Alto, CA 107 3301
Wang, David T San Jose, CA 149 3706
Weber, Frederick Daniel San Jose, CA 88 3037

Cited Art Landscape

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5,530,836 Method and apparatus for multiple memory bank selection 70 1994
5,513,135 Synchronous memory packaged in single/dual in-line memory module and method of fabrication 352 1994
5,563,086 Integrated memory cube, structure and fabrication 120 1995
5,872,907 Fault tolerant design for identification of AC defects including variance of cycle time to maintain system operation 80 1995
5,590,071 Method and apparatus for emulating a high capacity DRAM 90 1995
5,680,342 Memory module package with address bus buffering 69 1996
5,692,121 Recovery unit for mirrored processors 89 1996
5,802,395 High density memory modules with improved data bus performance 135 1996
5,702,984 Integrated mulitchip memory module, structure and fabrication 117 1996
5,870,350 High performance, high bandwidth memory bus architecture utilizing SDRAMs 186 1997
5,943,254 Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes 116 1997
5,963,464 Stackable memory card 129 1998
6,070,217 High density memory module with in-line bus switches being enabled in response to read/write selection state of connected RAM banks to improve data bus performance 107 1998
6,327,664 Power management on a memory card having a signal processing element 70 1999
6,453,434 Dynamically-tunable memory controller 69 2001
6,490,161 Peripheral land grid array package with improved thermal performance 105 2002
6,968,416 Method, system, and program for processing transaction requests during a pendency of a delayed read request in a system including a bus, a target device and devices capable of accessing the target device over the bus 66 2002
7,480,774 Method for performing a command cancel function in a DRAM 63 2003
7,224,595 276-Pin buffered memory module with enhanced fault tolerance 122 2004
7,539,800 System, method and storage medium for providing segment level sparing 66 2004
7,366,947 High reliability memory module with a fault tolerant address and command bus 64 2006
2008/0098,277 HIGH DENSITY HIGH RELIABILITY MEMORY MODULE WITH POWER GATING AND A FAULT TOLERANT ADDRESS AND COMMAND BUS 92 2006
 
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6,751,113 Arrangement of integrated circuits in a memory module 168 2002
6,930,900 Arrangement of integrated circuits in a memory module 61 2004
6,930,903 Arrangement of integrated circuits in a memory module 63 2004
2005/0018,495 ARRANGEMENT OF INTEGRATED CIRCUITS IN A MEMORY MODULE 106 2004
6,873,534 Arrangement of integrated circuits in a memory module 91 2004
7,286,436 High-density memory module utilizing low-density memory components 82 2005
7,254,036 High density memory module using stacked printed circuit boards 73 2005
7,289,386 Memory module decoder 93 2005
7,532,537 Memory module with a circuit providing load isolation and memory domain translation 93 2006
2006/0262,586 Memory module with a circuit providing load isolation and memory domain translation 80 2006
7,619,912 Memory module decoder 81 2007
 
AT&T IPM CORP. (1)
5,513,339 Concurrent fault simulation of circuits with both logic elements and functional circuits 149 1994
 
LSI LOGIC CORPORATION (1)
5,640,337 Method and apparatus for interim in-situ testing of an electronic system with an inchoate ASIC 81 1996
 
CISCO TECHNOLOGY, INC. (1)
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FUJITSU LIMITED (3)
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6,664,625 Mounting structure of a semiconductor device 60 2002
7,085,941 Clock control apparatus and method, for a memory controller, that processes a block access into single continuous macro access while minimizing power consumption 69 2003
 
GODO KAISHA IP BRIDGE 1 (1)
5,973,392 Stacked carrier three-dimensional memory module and semiconductor device using the same 91 1998
 
INFINEON TECHNOLOGIES AG (17)
6,526,484 Methods and apparatus for reordering of the memory requests to achieve higher average utilization of the command and data bus 85 1999
6,438,057 DRAM refresh timing adjustment device, system and method 130 2001
7,228,264 Program-controlled unit 61 2002
6,614,700 Circuit configuration with a memory array 61 2002
6,665,224 Partial refresh for synchronous dynamic random access memory (SDRAM) circuits 71 2002
7,028,234 Method of self-repairing dynamic random access memory 63 2002
7,035,150 Memory device with column select being variably delayed 67 2002
6,986,118 Method for controlling semiconductor chips and control apparatus 65 2003
7,231,562 Memory module, test system and method for testing one or a plurality of memory modules 133 2004
6,894,933 Buffer amplifier architecture for semiconductor memory circuits 68 2004
7,061,784 Semiconductor memory module 65 2004
7,200,021 Stacked DRAM memory chip for a dual inline memory module (DIMM) 123 2004
7,266,639 Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM) 86 2004
2006/0129,712 Buffer chip for a multi-rank dual inline memory module (DIMM) 69 2004
2006/0129,740 Memory device, memory controller and method for operating the same 56 2004
7,079,441 Methods and apparatus for implementing a power down in a memory device 67 2005
2006/0294,295 DRAM chip device well-communicated with flash memory chip and multi-chip package comprising such a device 97 2005
 
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5,257,233 Low power memory module using restricted RAM activation 80 1990
5,278,796 Temperature-dependent DRAM refresh circuit 173 1991
5,282,177 Multiple register block write method and circuit for video DRAMs 98 1992
5,526,320 Burst EDO memory device 172 1994
5,610,864 Burst EDO memory device with maximized write cycle timing 117 1995
5,652,724 Burst EDO memory device having pipelined output buffer 115 1995
5,675,549 Burst EDO memory device address counter 105 1995
5,598,376 Distributed write data drivers for burst access memories 141 1995
5,729,503 Address transition detection on a synchronous design 99 1995
5,724,288 Data communication for memory 65 1995
5,668,773 Synchronous burst extended data out DRAM 98 1995
5,682,354 CAS recognition in burst extended data out DRAM 88 1995
5,721,859 Counter control circuit in a burst memory 96 1995
5,604,714 DRAM having multiple column address strobe operation 76 1995
5,640,364 Self-enabling pulse trapping circuit 103 1995
5,729,504 Continuous burst edo memory device 98 1995
5,627,791 Multiple bank memory with auto refresh to specified bank 220 1996
5,661,695 Burst EDO memory device 88 1996
5,802,010 Burst EDO memory device 78 1996
5,917,758 Adjustable output driver circuit 109 1996
5,703,813 DRAM having multiple column address strobe operation 72 1996
5,696,732 Burst EDO memory device 80 1996
5,706,247 Self-enabling pulse-trapping circuit 90 1996
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5,923,611 Memory having a plurality of external clock signal inputs 81 1996
5,838,177 Adjustable output driver circuit having parallel pull-up and pull-down elements 162 1997
5,757,703 Distributed write data drivers for burst access memories 86 1997
5,717,654 Burst EDO memory device with maximized write cycle timing 90 1997
5,812,488 Synchronous burst extended data out dram 80 1997
5,870,347 Multi-bank memory input/output line selection 115 1997
5,875,142 Integrated circuit with temperature detector 109 1997
5,831,931 Address strobe recognition in a memory device 68 1997
5,946,265 Continuous burst EDO memory device 93 1997
5,831,932 Self-enabling pulse-trapping circuit 72 1997
5,850,368 Burst EDO memory address counter 83 1997
6,002,613 Data communication for memory 64 1997
5,963,504 Address transition detection in a synchronous design 88 1997
6,016,282 Clock vernier adjustment 266 1998
6,069,504 Adjustable output driver circuit having parallel pull-up and pull-down elements 95 1998
6,029,250 Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same 378 1998
6,101,612 Apparatus for aligning clock and data signals received from a RAM 105 1998
6,108,795 Method for aligning clock and data signals received from a RAM 101 1998
6,044,032 Addressing scheme for a double data rate SDRAM 108 1998
6,002,627 Integrated circuit with temperature detector 96 1999
6,026,050 Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same 183 1999
6,326,810 Adjustable output driver circuit 73 1999
6,084,434 Adjustable output driver circuit 77 1999
6,453,402 Method for synchronizing strobe and data signals from a RAM 82 1999
6,307,769 Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices 83 1999
6,260,154 Apparatus for aligning clock and data signals received from a RAM 69 2000
6,330,683 Method for aligning clock and data signals received from a RAM 80 2000
6,356,500 Reduced power DRAM device and method 105 2000
6,496,440 Method and system for accessing rows in multiple memory banks within an integrated circuit 74 2001
6,801,989 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same 81 2001
6,437,600 Adjustable output driver circuit 71 2001
6,754,129 Memory module with integrated bus termination 68 2002
7,149,824 Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction 62 2002
7,120,727 Reconfigurable memory module and method 155 2003
7,428,644 System and method for selective memory module power management 79 2003
7,210,059 System and method for on-board diagnostics of memory modules 99 2003
6,862,202 Low power memory module using restricted device activation 57 2003
2006/0041,730 Memory command delay balancing in a daisy-chained memory topology 83 2004
7,046,538 Memory stacking system and method 78 2004
7,245,541 Active termination control 66 2005
7,269,042 Memory stacking system and method 84 2006
7,437,579 System and method for selective memory module power management 69 2006
 
EMC CORPORATION (3)
5,798,961 Non-volatile memory module 102 1994
5,742,792 Remote data mirroring 685 1996
6,058,451 Method and apparatus for refreshing a non-clocked memory 68 1997
 
INTEL CORPORATION (44)
5,388,265 Method and apparatus for placing an integrated circuit chip in a reduced power consumption state 188 1993
5,860,106 Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem 177 1995
5,692,202 System, apparatus, and method for managing power in a computer system 98 1995
6,279,069 Interface for flash EEPROM memory arrays 307 1996
5,884,088 System, apparatus and method for managing power in a computer system 100 1997
5,835,435 Method and apparatus for dynamically placing portions of a memory in a reduced power consumtion state 112 1997
6,298,426 Controller configurable for use with multiple memory organizations 106 1997
6,968,419 Memory module having a memory module controller controlling memory transactions for a plurality of memory devices 103 1998
6,970,968 Memory module controller for providing an interface between a system memory controller and a plurality of memory devices on a memory module 145 1998
6,233,650 Using FET switches for large memory arrays 145 1998
6,199,151 Apparatus and method for storing a device row indicator for use in a subsequent page-miss memory cycle 60 1998
6,587,912 Method and apparatus for implementing multiple memory buses on a memory module 297 1998
6,038,673 Computer system with power management scheme for DRAM devices 80 1998
6,442,698 Method and apparatus for power management in a memory subsystem 90 1998
6,457,095 Method and apparatus for synchronizing dynamic random access memory exiting from a low power state 75 1999
6,621,760 Method, apparatus, and system for high speed data transfer using source synchronous data strobe 69 2000
6,564,285 Synchronous interface for a nonvolatile memory 147 2000
6,356,105 Impedance control system for a center tapped termination bus 108 2000
6,317,352 Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules 320 2000
6,487,102 Memory module having buffer for isolating stacked memory devices 177 2000
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6,820,163 Buffering data transfer between a chipset and memory modules 83 2000
6,862,653 System and method for controlling data flow direction in a memory system 63 2000
6,618,791 System and method for controlling power states of a memory device via detection of a chip select signal 91 2000
6,785,767 Hybrid mass storage system and method with two different types of storage medium 112 2000
6,563,337 Driver impedance control mechanism 74 2001
6,820,169 Memory control with lookahead power management 74 2001
2003/0105,932 Emulation of memory clock enable pin and use of chip select for memory power control 69 2001
6,714,891 Method and apparatus for thermal management of a power supply to a high performance processor in a computer system 86 2001
6,799,241 Method for dynamically adjusting a memory page closing policy 105 2002
7,024,518 Dual-port buffer-to-memory interface 88 2002
6,795,899 Memory system with burst length shorter than prefetch length 193 2002
7,103,730 Method, system, and apparatus for reducing power consumption of a memory 84 2002
6,639,820 Memory buffer arrangement 76 2002
6,747,887 Memory module having buffer for isolating stacked memory devices 81 2002
6,839,290 Method, apparatus, and system for high speed data transfer using source synchronous data strobe 65 2003
2005/0108,460 Partial bank DRAM refresh 72 2003
7,127,567 Performing memory RAS operations over a point-to-point interconnect 64 2003
2005/0138,267 Integral memory buffer and serial presence detect capability for fully-buffered memory modules 177 2003
7,085,152 Memory system segmented power supply and control 68 2003
7,133,960 Logical to physical address mapping of chip selects 96 2003
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2005/0204,111 Command scheduling for dual-data-rate two (DDR2) memory devices 63 2004
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2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
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* Cited By Examiner

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Patent Info (Count) # Cites Year
 
RAMBUS INC. (2)
* 8,537,601 Memory controller with selective data transmission delay 1 2012
* 2012/0287,725 MEMORY CONTROLLER WITH SELECTIVE DATA TRANSMISSION DELAY 1 2012
 
P4tents1, LLC (1)
8,930,647 Multiple class memory systems 1 2012
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