Memory refresh apparatus and method

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8077535
APP PUB NO 20080025122A1
SERIAL NO

11461437

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A system and method are provided. The system and method simulate a DRAM memory circuit using an interface circuit connected to a plurality of other DRAM memory circuits. In response to the receipt of a refresh control signal, a first refresh control signal is sent to a first subset of the plurality of other DRAM memory circuits and a second refresh control signal is sent to a second subset of the plurality of other DRAM memory circuits.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
GOOGLE INC.MOUNTAIN VIEW, CA22948

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rajan, Suresh Natarajan San Jose, US 79 4888
Schakel, Keith R San Jose, US 63 4369
Smith, Michael John Sebastian Palo Alto, US 75 4623
Wang, David T San Jose, US 92 5087
Weber, Frederick Daniel San Jose, US 54 4085

Cited Art Landscape

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* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
PATENTS1, LLC (1)
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SAMSUNG ELECTRONICS CO., LTD. (1)
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RAMBUS INC. (3)
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P4TENTS1, LLC (9)
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9176671 Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system 0 2015
9170744 Computer program product for controlling a flash/DRAM/embedded DRAM-equipped system 0 2015
9158546 Computer program product for fetching from a first physical memory between an execution of a plurality of threads associated with a second physical memory 1 2015
* Cited By Examiner

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