US Patent No: 8,077,535 - Analytics, PDF, Full Text and PAIR Access

Number of patents in Portfolio can not be more than 2000

Memory refresh apparatus and method

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A system and method are provided. The system and method simulate a DRAM memory circuit using an interface circuit connected to a plurality of other DRAM memory circuits. In response to the receipt of a refresh control signal, a first refresh control signal is sent to a first subset of the plurality of other DRAM memory circuits and a second refresh control signal is sent to a second subset of the plurality of other DRAM memory circuits.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
GOOGLE INC.MOUNTAIN VIEW, CA16222

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rajan, Suresh Natarajan San Jose, US 79 4764
Schakel, Keith R San Jose, US 63 4255
Smith, Michael John Sebastian Palo Alto, US 75 4509
Wang, David T San Jose, US 92 4942
Weber, Frederick Daniel San Jose, US 54 3975

Cited Art Landscape

Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (4)
5,252,807 Heated plate rapid thermal processor 223 1991
6,091,251 Discrete die burn-in for nonpackaged die 113 1997
6,757,751 High-speed, multiple-bank, stacked, and PCB-mounted memory module 88 2000
2002/0064,073 DRAM MODULE AND METHOD OF USING SRAM TO REPLACE DAMAGED DRAM CELL 69 2000
 
HOECHST MARION ROUSSEL, INC. (1)
5,962,435 Method of lowering serum cholesterol levels with 2,6-di-alkyl-4-silyl-phenols 54 1997
 
SONY CORPORATION (1)
7,233,541 Storage device 67 2005
 
KYOEI SANGYO CO., LTD. (1)
6,512,392 Method for testing semiconductor devices 73 2000
 
VULCAN VENTURES, INC. (1)
6,526,471 Method and apparatus for a high-speed memory subsystem 86 1998
 
FormFactor, Inc. (1)
6,429,029 Concurrent design and subsequent partitioning of product and test die 163 1998
 
SAMSUNG ELECTRONICS CO., LTD. (23)
5,845,108 Semiconductor memory device using asynchronous signal 99 1996
6,078,546 Synchronous semiconductor memory device with double data rate scheme 118 1998
6,208,168 Output driver circuits having programmable pull-up and pull-down capability for driving variable loads 78 1998
6,034,916 Data masking circuits and methods for integrated circuit memory devices, including data strobe signal synchronization 102 1998
6,526,473 Memory module system for controlling data input and output by connecting selected memory modules to a data line 89 1999
6,381,188 DRAM capable of selectively performing self-refresh operation for memory bank 85 2000
6,262,938 Synchronous DRAM having posted CAS latency and method for controlling CAS latency 90 2000
6,362,656 Integrated circuit memory devices having programmable output driver circuits therein 78 2001
6,452,826 Memory module system 126 2001
6,498,766 Integrated circuit memory devices that utilize indication signals to increase reliability of reading and writing operations and methods of operating same 95 2001
6,459,651 Semiconductor memory device having data masking pin and memory system including the same 72 2001
6,590,822 System and method for performing partial array self-refresh operation in a semiconductor memory device 98 2001
6,560,158 Power down voltage control method and apparatus 78 2001
6,754,132 Devices and methods for controlling active termination resistors in a memory system 83 2002
6,762,948 Semiconductor memory device having first and second memory architecture and memory system using the same 75 2002
6,819,602 Multimode data buffer and method for controlling propagation delay time 78 2002
6,650,594 Device and method for selecting power down exit 101 2002
7,058,776 Asynchronous memory using source synchronous transfer and system employing the same 77 2003
6,819,617 System and method for performing partial array self-refresh operation in a semiconductor memory device 75 2003
7,215,561 Semiconductor memory system having multiple system data buses 71 2003
6,862,249 Devices and methods for controlling active termination resistors in a memory system 64 2004
2004/0196,732 Multi-stage output multiplexing circuits and methods for double data rate synchronous memory devices 67 2004
2005/0224,948 Semiconductor device package having buffered memory module and method thereof 62 2005
 
BROOKE, LAWRENCE L. (1)
7,126,399 Memory interface phase-shift circuitry to support multiple frequency ranges 73 2004
 
XILINX, INC. (1)
6,917,219 Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice 168 2003
 
IRVINE SENSORS CORPORATION (3)
4,525,921 High-density electronic processing package-structure and fabrication 214 1983
4,646,128 High-density electronic processing package--structure and fabrication 156 1985
4,764,846 High density electronic package comprising stacked sub-modules 229 1987
 
NXP B.V. (1)
* 5,193,072 Hidden refresh of a dynamic random access memory 100 1990
 
UNIRAM TECHNOLOGY, INC. (1)
6,216,246 Methods to make DRAM fully compatible with SRAM using error correction code (ECC) mechanism 126 1997
 
UNITED MICROELECTRONICS CORP. (1)
5,752,045 Power conservation in synchronous SRAM cache memory blocks of a computer system 105 1995
 
CALLAHAN CELLULAR L.L.C. (2)
5,953,215 Apparatus and method for improving computer memory speed and capacity 201 1998
7,205,789 Termination arrangement for high speed data rate multi-drop data bit connections 63 2005
 
RENESAS ELECTRONICS CORPORATION (13)
5,220,672 Low power consuming digital circuit device 100 1991
6,453,400 Semiconductor integrated circuit device 71 1998
6,252,807 Memory device with reduced power consumption when byte-unit accessed 59 1999
2002/0129,298 Method of and apparatus for testing CPU built-in RAM mixed LSI 0 2001
* 6,922,371 Semiconductor storage device 68 2002
6,791,877 Semiconductor device with non-volatile memory and random access memory 104 2002
6,597,617 Semiconductor device with reduced current consumption in standby state 69 2002
* 6,650,588 Semiconductor memory module and register buffer device for use in the same 73 2002
7,136,978 System and method for using dynamic random access memory and flash memory 75 2003
* 6,850,449 Semiconductor memory device having mode storing one bit data in two memory cells and method of controlling same 79 2003
7,613,880 Memory module, memory system, and information device 77 2003
2006/0041,711 Memory module, memory system, and information device 85 2003
7,296,754 IC card module 78 2005
 
BROADCOM CORPORATION (1)
6,658,016 Packet switching fabric having a segmented ring with token based resource control protocol and output queuing control 98 2000
 
UNITED MEMORIES, INC. (1)
6,392,304 Multi-chip memory apparatus and associated method 95 1998
 
SANDISK IL LTD. (1)
2005/0027,928 SDRAM memory device with an embedded NAND flash controller 113 2003
 
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. (2)
5,926,435 Apparatus for saving power consumption in semiconductor memory devices 69 1997
6,772,359 Clock control circuit for Rambus DRAM 67 2000
 
POLARIS INNOVATIONS LIMITED (13)
6,526,484 Methods and apparatus for reordering of the memory requests to achieve higher average utilization of the command and data bus 93 1999
6,438,057 DRAM refresh timing adjustment device, system and method 138 2001
6,614,700 Circuit configuration with a memory array 63 2002
6,665,224 Partial refresh for synchronous dynamic random access memory (SDRAM) circuits 73 2002
7,028,234 Method of self-repairing dynamic random access memory 67 2002
7,035,150 Memory device with column select being variably delayed 69 2002
6,986,118 Method for controlling semiconductor chips and control apparatus 67 2003
7,231,562 Memory module, test system and method for testing one or a plurality of memory modules 136 2004
6,894,933 Buffer amplifier architecture for semiconductor memory circuits 70 2004
7,061,784 Semiconductor memory module 68 2004
7,200,021 Stacked DRAM memory chip for a dual inline memory module (DIMM) 133 2004
7,266,639 Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM) 89 2004
7,079,441 Methods and apparatus for implementing a power down in a memory device 71 2005
 
INTERMEDICS, INC. (1)
5,963,429 Printed circuit substrate with cavities for encapsulating integrated circuits 111 1997
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (2)
6,766,469 Hot-replace of memory 98 2001
7,234,081 Memory module with testing logic 66 2004
 
OCZ TECHNOLOGY (1)
2005/0278,474 Method of increasing DDR memory bandwidth in DDR SDRAM modules 67 2005
 
OVID DATA CO. LLC (2)
5,843,807 Method of manufacturing an ultra-high density warp-resistant memory module 78 1996
7,026,708 Low profile chip scale stacking system and method 64 2003
 
GLOBALFOUNDRIES INC. (4)
6,295,572 Integrated SCSI and ethernet controller on a PCI local bus 68 1994
5,502,333 Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit 242 1994
5,943,254 Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes 118 1997
7,480,774 Method for performing a command cancel function in a DRAM 66 2003
 
OKI ELECTRIC INDUSTRY CO., LTD. (1)
2005/0283,572 Semiconductor integrated circuit and power-saving control method thereof 62 2005
 
RAMBUS INC. (44)
5,748,914 Protocol for communication with dynamic memory 153 1995
5,841,580 Integrated circuit I/O using a high performance bus interface 95 1997
5,954,804 Synchronous memory device having an internal register 140 1997
5,915,105 Integrated circuit I/O using a high performance bus interface 129 1997
6,075,730 High performance cost optimized memory with delayed memory writes 136 1998
6,075,744 Dram core refresh with reduced spike current 77 1998
5,953,263 Synchronous memory device having a programmable register and method of controlling same 123 1998
6,038,195 Synchronous memory device having a delay time register and method of operating same 107 1998
6,035,365 Dual clocked synchronous memory device having a delay time register and method of operating same 99 1998
6,101,152 Method of operating a synchronous memory device 150 1998
6,032,214 Method of operating a synchronous memory device having a variable data output length 105 1999
6,034,918 Method of operating a memory having a variable data output length and a programmable register 102 1999
5,995,443 Synchronous memory device 107 1999
6,032,215 Synchronous memory device utilizing two external clocks 64 1999
6,452,863 Method of operating a memory device having a variable data input length 66 2000
6,182,184 Method of operating a memory device having a variable data input length 71 2000
6,260,097 Method and apparatus for controlling a synchronous memory device 111 2000
6,378,020 System having double data transfer rate and intergrated circuit therefor 74 2000
6,266,292 DRAM core refresh with reduced spike current 69 2000
6,343,042 DRAM core refresh with reduced spike current 66 2000
6,266,285 Method of operating a memory device having write latency 115 2000
6,314,051 Memory device having write latency 124 2000
6,426,916 Memory device having a variable data output length and a programmable register 75 2001
6,697,295 Memory device having a programmable register 66 2001
6,751,696 Memory device having a programmable register 72 2001
6,496,897 Semiconductor memory device which receives write masking information 121 2001
6,701,446 Power control system for synchronous memory device 111 2001
6,493,789 Memory device which receives write masking and automatic precharge information 123 2001
6,564,281 Synchronous memory device having automatic precharge 67 2001
6,546,446 Synchronous memory device having automatic precharge 63 2001
6,807,598 Integrated circuit device having double data rate capability 70 2002
6,597,616 DRAM core refresh with reduced spike current 63 2002
6,584,037 Memory device which samples data after an amount of time transpires 104 2002
7,043,599 Dynamic memory supporting simultaneous refresh and data-access transactions 148 2002
7,363,422 Configurable width buffered module 85 2004
7,269,708 Memory controller for non-homogenous memory system 107 2004
7,003,639 Memory controller with power management logic 77 2004
7,010,642 System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices 78 2004
7,000,062 System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices 111 2005
7,003,618 System featuring memory modules that include an integrated circuit buffer devices 67 2005
7,581,121 System for a memory device having a power down mode and method 61 2005
7,464,225 Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology 88 2005
2007/0279,084 INTEGRATED CIRCUIT WITH GRADUATED ON-DIE TERMINATION 61 2006
2007/0088,995 SYSTEM INCLUDING A BUFFERED MEMORY MODULE 95 2006
 
Anamartic Limited (1)
5,072,424 Wafer-scale integrated circuit memory 68 1987
 
SUN MICROSYSTEMS, INC. (1)
2006/0112,219 Functional partitioning method for providing modular data storage systems 130 2004
 
Cascade Semiconductor Corporation (1)
2004/0047,228 Asynchronous hidden refresh of semiconductor memory 69 2003
 
INTELLECTUAL VENTURES I LLC (1)
5,787,457 Cached synchronous DRAM architecture allowing concurrent DRAM operations 191 1996
 
National Semiconductor Corporation (6)
4,887,240 Staggered refresh for dram array 72 1987
5,606,710 Multiple chip package processor having feed through paths on one die 80 1994
5,566,344 In-system programming architecture for a multiple chip processor 76 1995
5,581,779 Multiple chip processor architecture with memory interface control register for in-system programming 71 1995
5,623,686 Non-volatile memory control and data loading architecture for multiple chip processor 69 1995
5,781,766 Programmable compensating device to optimize performance in a DRAM controller chipset 86 1996
 
Kingston Technology Corporation (2)
7,317,250 High density memory card assembly 63 2004
7,474,576 Repairing Advanced-Memory Buffer (AMB) with redundant memory buffer for repairing DRAM on a fully-buffered memory-module 66 2008
 
MOSYS, INC. (2)
5,498,886 Circuit module redundancy architecture 88 1994
5,843,799 Circuit module redundancy architecture process 104 1997
 
Advanced Interconnect Solutions (1)
2002/0015,340 Method and apparatus for memory module circuit interconnection 67 2001
 
Texas Instruments Incorporated (3)
6,421,754 System management mode circuits, systems and methods 130 1995
5,802,555 Computer system including a refresh controller circuit having a row address strobe multiplexer and associated method 122 1997
5,956,233 High density single inline memory module 96 1997
 
VACHELLIA, LLC (1)
6,338,113 Memory module system having multiple memory modules 142 1998
 
TRAN, DAVID N. (1)
2006/0117,160 Method to consolidate memory usage to reduce power consumption 80 2004
 
VIA TECHNOLOGIES, INC. (4)
2001/0003,198 Method for timing setting of a system memory 103 2000
7,007,175 Motherboard with reduced power consumption 97 2001
2005/0289,317 METHOD AND RELATED APPARATUS FOR ACCESSING MEMORY 101 2005
7,441,064 Flexible width data protocol 55 2006
 
MICRON TECHNOLOGY, INC. (23)
4,899,107 Discrete die burn-in for nonpackaged die 224 1988
5,241,266 Built-in test circuit connection for wafer level burnin and testing of individual dies 146 1992
5,408,190 Testing apparatus having substrate interconnect for discrete die burn-in for nonpackaged die 204 1993
5,907,512 Mask write enablement for memory devices which permits selective masked enablement of plural segments 75 1993
5,966,724 Synchronous memory device with dual page and burst mode operations 267 1996
5,661,677 Circuit and method for on-board programming of PRD Serial EEPROMS 134 1996
5,903,500 1.8 volt output buffer on flash memories 75 1997
5,901,105 Dynamic random access memory having decoding circuitry for partial memory blocks 119 1997
5,859,792 Circuit for on-board programming of PRD serial EEPROMs 75 1997
5,963,463 Method for on-board programming of PRD serial EEPROMS 79 1997
6,111,812 Method and apparatus for adjusting control signal timing in a memory device 98 1999
6,317,381 Method and system for adaptively adjusting control signal timing in a memory device 80 1999
6,304,511 Method and apparatus for adjusting control signal timing in a memory device 76 2000
6,243,282 Apparatus for on-board programming of serial EEPROMs 73 2000
6,731,527 Architecture for a semiconductor memory device for minimizing interference and cross-coupling between control signal lines and power lines 69 2001
6,912,778 Methods of fabricating full-wafer silicon probe cards for burn-in and testing of semiconductor devices 72 2001
6,418,034 Stacked printed circuit board memory module and method of augmenting memory therein 71 2001
6,771,526 Method and apparatus for data transfer 71 2002
6,847,582 Low skew clock input buffer and method 89 2003
2006/0010,339 Memory system and method having selective ECC during low power refresh 105 2004
7,149,145 Delay stage-interweaved analog DLL/PLL 67 2004
6,947,341 Integrated semiconductor memory chip with presence detect data capability 66 2004
7,573,136 Semiconductor device assemblies and packages including multiple semiconductor device components 76 2005
 
ULTRATERA CORPORATION (1)
6,713,856 Stacked chip package with enhanced thermal conductivity 76 2002
 
SUPER TALENT TECHNOLOGY, CORP. (1)
7,243,185 Flash memory system with a high-speed flash controller 76 2004
 
LG SEMICON CO., LTD. (1)
5,905,688 Auto power down circuit for a semiconductor memory device 69 1998
 
TWITTER, INC. (1)
6,381,668 Address mapping for system memory 106 1998
 
SOCIONEXT INC. (6)
6,014,339 Synchronous DRAM whose power consumption is minimized 99 1997
6,353,561 Semiconductor integrated circuit and method for controlling the same 69 1999
6,594,770 Semiconductor integrated circuit device 72 1999
6,898,683 Clock synchronized dynamic memory and clock synchronized integrated circuit 76 2001
7,302,598 Apparatus to reduce the internal frequency of an integrated circuit by detecting a drop in the voltage and frequency 75 2004
6,845,055 Semiconductor memory capable of transitioning from a power-down state in a synchronous mode to a standby state in an asynchronous mode without setting by a control register 76 2004
 
SRC COMPUTERS, INC. (1)
2004/0236,877 Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM) 180 2004
 
PS4 LUXCO S.A.R.L. (1)
* 5,969,996 Semiconductor memory device and memory system 70 1998
 
TANISYS TECHNOLOGY, INC. (1)
5,995,424 Synchronous memory test system 114 1997
 
AMETEK, INC., COMPUTER RESEARCH DIVISION (1)
4,937,791 High performance dynamic ram interface 95 1988
 
SYNOLOGY INCORPORATED (1)
6,952,794 Method, system and apparatus for scanning newly added disk drives and automatically updating RAID configuration and rebuilding RAID data 118 2002
 
GOOGLE INC. (62)
5,519,832 Method and apparatus for displaying module diagnostic results 111 1995
6,618,267 Multi-level electronic package and method for making same 100 1998
7,515,453 Integrated memory core and memory interface circuit 67 2006
2007/0050,530 Integrated memory core and memory interface circuit 89 2006
7,580,312 Power saving system and method for use with a plurality of memory circuits 75 2006
7,609,567 System and method for simulating an aspect of a memory circuit 77 2006
7,724,589 System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits 73 2006
2008/0025,108 SYSTEM AND METHOD FOR DELAYING A SIGNAL COMMUNICATED FROM A SYSTEM TO AT LEAST ONE OF A PLURALITY OF MEMORY CIRCUITS 74 2006
2008/0025,122 MEMORY REFRESH SYSTEM AND METHOD 73 2006
2008/0025,136 SYSTEM AND METHOD FOR STORING AT LEAST A PORTION OF INFORMATION RECEIVED IN ASSOCIATION WITH A FIRST OPERATION FOR USE IN PERFORMING A SECOND OPERATION 74 2006
2008/0025,137 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 81 2006
2008/0027,702 SYSTEM AND METHOD FOR SIMULATING A DIFFERENT NUMBER OF MEMORY CIRCUITS 74 2006
2008/0028,135 MULTIPLE-COMPONENT MEMORY INTERFACE SYSTEM AND METHOD 88 2006
2008/0031,072 POWER SAVING SYSTEM AND METHOD FOR USE WITH A PLURALITY OF MEMORY CIRCUITS 71 2006
7,379,316 Methods and apparatus of stacking DRAMs 105 2006
2007/0058,471 Methods and apparatus of stacking DRAMs 80 2006
7,386,656 Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit 78 2006
7,392,338 Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits 73 2006
7,472,220 Interface circuit system and method for performing power management operations utilizing power management signals 76 2006
7,590,796 System and method for power management in memory systems 76 2006
2008/0031,030 System and method for power management in memory systems 96 2006
2008/0082,763 APPARATUS AND METHOD FOR POWER MANAGEMENT OF MEMORY CIRCUITS BY A SYSTEM OR COMPONENT THEREOF 79 2006
7,581,127 Interface circuit system and method for performing power saving operations during a command-related latency 74 2006
2008/0037,353 Interface circuit system and method for performing power saving operations during a command-related latency 70 2006
2008/0027,697 MEMORY CIRCUIT SIMULATION SYSTEM AND METHOD WITH POWER SAVING CAPABILITIES 72 2006
2008/0027,703 MEMORY CIRCUIT SIMULATION SYSTEM AND METHOD WITH REFRESH CAPABILITIES 71 2006
2008/0123,459 COMBINED SIGNAL DELAY AND POWER SAVING SYSTEM AND METHOD FOR USE WITH A PLURALITY OF MEMORY CIRCUITS 72 2006
2008/0086,588 System and Method for Increasing Capacity, Performance, and Flexibility of Flash Storage 76 2006
2007/0195,613 Memory module with memory stack and interface with enhanced capabilities 92 2007
2008/0126,690 Memory module with memory stack 100 2007
2007/0192,563 SYSTEM AND METHOD FOR TRANSLATING AN ADDRESS ASSOCIATED WITH A COMMAND COMMUNICATED BETWEEN A SYSTEM AND MEMORY CIRCUITS 83 2007
2007/0204,075 SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS 83 2007
2008/0056,014 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 75 2007
2008/0062,773 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 75 2007
2008/0010,435 MEMORY SYSTEMS AND MEMORY MODULES 108 2007
2008/0028,136 METHOD AND APPARATUS FOR REFRESH MANAGEMENT OF MEMORY MODULES 73 2007
2008/0028,137 Method and Apparatus For Refresh Management of Memory Modules 79 2007
2008/0103,753 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 82 2007
2008/0104,314 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 77 2007
2008/0109,206 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 77 2007
2008/0109,595 SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS 81 2007
2008/0109,597 METHOD AND APPARATUS FOR REFRESH MANAGEMENT OF MEMORY MODULES 78 2007
2008/0109,598 Method and apparatus for refresh management of memory modules 78 2007
2008/0120,443 SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS 79 2007
2008/0126,687 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 77 2007
2008/0126,688 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 77 2007
2008/0126,689 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 77 2007
2008/0126,692 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 78 2007
2008/0133,825 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 77 2007
2009/0024,789 MEMORY CIRCUIT SYSTEM AND METHOD 93 2007
2009/0024,790 MEMORY CIRCUIT SYSTEM AND METHOD 75 2007
2008/0115,006 SYSTEM AND METHOD FOR ADJUSTING THE TIMING OF SIGNALS ASSOCIATED WITH A MEMORY SYSTEM 95 2007
7,599,205 Methods and apparatus of stacking DRAMs 79 2008
2008/0170,425 METHODS AND APPARATUS OF STACKING DRAMS 88 2008
7,730,338 Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits 73 2008
7,761,724 Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit 72 2008
2008/0239,857 INTERFACE CIRCUIT SYSTEM AND METHOD FOR PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH ONLY A PORTION OF A MEMORY CIRCUIT 72 2008
2008/0239,858 INTERFACE CIRCUIT SYSTEM AND METHOD FOR AUTONOMOUSLY PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH A PLURALITY OF MEMORY CIRCUITS 72 2008
2009/0216,939 Emulation of abstracted DIMMs using abstracted DRAMs 63 2009
2009/0285,031 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 71 2009
2009/0290,442 METHOD AND CIRCUIT FOR CONFIGURING MEMORY CORE INTEGRATED CIRCUIT DIES WITH MEMORY INTERFACE INTEGRATED CIRCUIT DIES 61 2009
2010/0020,585 METHODS AND APPARATUS OF STACKING DRAMS 64 2009
 
SYNOPSYS, INC. (1)
6,053,948 Method and apparatus using a memory model 79 1997
 
STORAGE TECHNOLOGY CORPORATION (1)
5,448,511 Memory stack with an integrated interconnect and mounting structure 248 1994
 
COMPUTERVISION CORPORATION (1)
4,888,687 Memory control system 64 1987
 
KONINKLIJKE PHILIPS ELECTRONICS N.V. (1)
2003/0046,431 Direct RTP delivery method and system over MPEG network 45 2002
 
SILICON INTEGRATED SYSTEMS CORP. (1)
2003/0158,995 Method for DRAM control with adjustable page size 91 2002
 
SHARP KABUSHIKI KAISHA (1)
6,233,192 Semiconductor memory device 69 1999
 
INTEGRATED DEVICE TECHNOLOGY, INC. (1)
7,079,446 DRAM interface circuits having enhanced skew, slew rate and impedance control 74 2004
 
INPHI CORPORATION (5)
6,980,021 Output buffer with time varying source impedance for driving capacitively-terminated transmission lines 81 2004
7,307,863 Programmable strength output buffer for RDIMM address register 77 2005
2007/0216,445 Output buffer with switchable output impedance 64 2006
2007/0247,194 Output buffer to drive AC-coupled terminated transmission lines 64 2006
7,408,393 Master-slave flip-flop and clocking scheme 65 2007
 
Viking Components (1)
6,222,739 High-density computer module with stacked parallel-plane packaging 152 1999
 
RPX CLEARINGHOUSE LLC (1)
6,445,591 Multilayer circuit board 83 2000
 
UNIVERSITY OF MARYLAND, BALTIMORE (1)
2006/0248,261 System and method for performing multi-rank command scheduling in DDR SDRAM memory systems 58 2006
 
SANDISK TECHNOLOGIES LLC (2)
* 6,711,043 Three-dimensional memory cache system 80 2002
7,173,863 Flash controller cache architecture 100 2004
 
NETWORK APPLIANCE, INC. (1)
7,218,566 Power management of memory via wake/sleep cycles 73 2005
 
AGILENT TECHNOLOGIES, INC. (1)
5,025,364 Microprocessor emulation system with memory mapping using variable definition and addressing of memory space 72 1987
 
Faraday Technology Corp. (1)
2002/0004,897 Data processing apparatus for executing multiple instruction sets 94 2000
 
CYPRESS SEMICONDUCTOR CORPORATION (5)
6,480,929 Pseudo-concurrency between a volatile memory and a non-volatile memory on a same data bus 91 1998
6,166,991 Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit 69 1999
6,363,031 Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit 68 2000
6,631,086 On-chip repair of defective address of core flash memory cells 84 2002
7,010,736 Address sequencer within BIST (Built-in-Self-Test) system 76 2002
 
HITACHI MAXELL, LTD. (1)
* 5,550,781 Semiconductor apparatus with two activating modes of different number of selected word lines at refreshing 67 1995
 
PANASONIC CORPORATION (1)
2005/0194,676 Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same 77 2005
 
CHEERTEK INC. (1)
2006/0112,214 Method for applying downgraded DRAM to an electronic device and the electronic device thereof 66 2005
 
EMC IP HOLDING COMPANY LLC (1)
6,058,451 Method and apparatus for refreshing a non-clocked memory 71 1997
 
North Carolina State University (1)
2006/0181,953 SYSTEMS, METHODS AND DEVICES FOR PROVIDING VARIABLE-LATENCY WRITE OPERATIONS IN MEMORY DEVICES 73 2005
 
BITMICRO NETWORKS (1)
2007/0288,686 Optimized placement policy for solid state storage devices 103 2006
 
HITACHI, LTD. (3)
6,430,103 Semiconductor integrated circuit device with memory banks and read buffer capable of storing data read out from one memory bank when data of another memory bank is outputting 81 2001
7,119,428 Semiconductor device 78 2004
7,409,492 Storage system using flash memory modules logically grouped for wear-leveling and RAID 141 2006
 
ORACLE AMERICA, INC. (9)
6,341,347 Thread switch logic in a multiple-thread processor 197 1999
6,414,868 Memory expansion module including multiple memory banks and a bank control circuit 121 1999
6,683,372 Memory expansion module with stacked memory packages and a serial storage unit 123 1999
6,658,530 High-performance memory module 85 2000
6,816,991 Built-in self-testing for double data rate input/output 86 2001
6,690,191 Bi-directional output buffer 86 2001
6,938,119 DRAM power management 134 2002
6,961,281 Single rank memory module for use in a two-rank memory module system 118 2003
7,496,777 Power throttling in a memory system 83 2005
 
Honda Giken Kogyo Kabushiki Kaisha (1)
2001/0052,756 Electric power steering apparatus 4 2001
 
KABUSHIKI KAISHA TOSHIBA (6)
5,083,266 Microcomputer which enters sleep mode for a predetermined period of time on response to an activity of an input/output device 279 1987
6,047,344 Semiconductor memory device with multiplied internal clock 68 1998
6,088,290 Semiconductor memory device having a power-down mode 88 1998
2002/0089,970 Multimedia private branch exchanger and private branch exchange system 64 2002
7,058,863 Semiconductor integrated circuit 72 2002
* 6,826,104 Synchronous semiconductor memory 68 2002
 
BELL TELEPHONE LABORATORIES, INCORPORATED (1)
4,592,019 Bus oriented LIFO/FIFO memory 89 1983
 
HYNIX SEMICONDUCTOR INC. (4)
6,646,939 Low power type Rambus DRAM 65 2002
6,724,684 Apparatus for pipe latch control circuit in synchronous memory device 76 2002
6,744,687 Semiconductor memory device with mode register and method for controlling deep power down mode therein 89 2002
2008/0159,027 SEMICONDUCTOR MEMORY DEVICE WITH MIRROR FUNCTION MODULE AND USING THE SAME 63 2007
 
WELLS FARGO FOOTHILL, INC. (1)
2006/0117,152 Transparent four rank memory module for standard two rank sub-systems 96 2004
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (25)
* 4,862,347 System for simulating memory arrays in a logic simulation machine 133 1986
4,884,237 Stacked double density memory module using industry standard memory chips 183 1989
4,922,451 Memory re-mapping in a microcomputer system 73 1989
5,502,667 Integrated multichip memory module structure 178 1993
5,561,622 Integrated memory cube structure 175 1993
5,530,836 Method and apparatus for multiple memory bank selection 72 1994
5,513,135 Synchronous memory packaged in single/dual in-line memory module and method of fabrication 361 1994
5,563,086 Integrated memory cube, structure and fabrication 125 1995
5,872,907 Fault tolerant design for identification of AC defects including variance of cycle time to maintain system operation 84 1995
5,590,071 Method and apparatus for emulating a high capacity DRAM 94 1995
5,680,342 Memory module package with address bus buffering 71 1996
5,692,121 Recovery unit for mirrored processors 91 1996
5,802,395 High density memory modules with improved data bus performance 138 1996
5,702,984 Integrated mulitchip memory module, structure and fabrication 123 1996
5,870,350 High performance, high bandwidth memory bus architecture utilizing SDRAMs 207 1997
5,963,464 Stackable memory card 136 1998
6,070,217 High density memory module with in-line bus switches being enabled in response to read/write selection state of connected RAM banks to improve data bus performance 114 1998
6,327,664 Power management on a memory card having a signal processing element 73 1999
6,453,434 Dynamically-tunable memory controller 71 2001
6,490,161 Peripheral land grid array package with improved thermal performance 109 2002
6,968,416 Method, system, and program for processing transaction requests during a pendency of a delayed read request in a system including a bus, a target device and devices capable of accessing the target device over the bus 68 2002
7,224,595 276-Pin buffered memory module with enhanced fault tolerance 134 2004
7,539,800 System, method and storage medium for providing segment level sparing 70 2004
7,366,947 High reliability memory module with a fault tolerant address and command bus 66 2006
2008/0098,277 HIGH DENSITY HIGH RELIABILITY MEMORY MODULE WITH POWER GATING AND A FAULT TOLERANT ADDRESS AND COMMAND BUS 119 2006
 
ADVANCED MICRO DEVICES, INC. (1)
5,559,990 Memories with burst mode access 99 1994
 
U.S. BANK NATIONAL ASSOCIATION (1)
2002/0034,068 Stacked printed circuit board memory module and method of augmenting memory therein 76 2001
 
Netlist, Inc. (11)
6,751,113 Arrangement of integrated circuits in a memory module 192 2002
6,930,900 Arrangement of integrated circuits in a memory module 83 2004
6,930,903 Arrangement of integrated circuits in a memory module 85 2004
2005/0018,495 ARRANGEMENT OF INTEGRATED CIRCUITS IN A MEMORY MODULE 130 2004
6,873,534 Arrangement of integrated circuits in a memory module 113 2004
7,286,436 High-density memory module utilizing low-density memory components 106 2005
7,254,036 High density memory module using stacked printed circuit boards 95 2005
7,289,386 Memory module decoder 117 2005
7,532,537 Memory module with a circuit providing load isolation and memory domain translation 124 2006
2006/0262,586 Memory module with a circuit providing load isolation and memory domain translation 85 2006
7,619,912 Memory module decoder 109 2007
 
AT&T IPM CORP. (1)
5,513,339 Concurrent fault simulation of circuits with both logic elements and functional circuits 151 1994
 
LSI LOGIC CORPORATION (1)
5,640,337 Method and apparatus for interim in-situ testing of an electronic system with an inchoate ASIC 83 1996
 
CISCO TECHNOLOGY, INC. (1)
7,606,245 Distributed packet processing architecture for network access servers 82 2005
 
FUJITSU LIMITED (3)
4,392,212 Semiconductor memory device with decoder for chip selection/write in 89 1980
6,664,625 Mounting structure of a semiconductor device 62 2002
7,085,941 Clock control apparatus and method, for a memory controller, that processes a block access into single continuous macro access while minimizing power consumption 71 2003
 
GODO KAISHA IP BRIDGE 1 (1)
5,973,392 Stacked carrier three-dimensional memory module and semiconductor device using the same 101 1998
 
INFINEON TECHNOLOGIES AG (4)
7,228,264 Program-controlled unit 63 2002
2006/0129,712 Buffer chip for a multi-rank dual inline memory module (DIMM) 72 2004
2006/0129,740 Memory device, memory controller and method for operating the same 59 2004
2006/0294,295 DRAM chip device well-communicated with flash memory chip and multi-chip package comprising such a device 119 2005
 
ALIBABA GROUP HOLDING LIMITED (2)
6,621,760 Method, apparatus, and system for high speed data transfer using source synchronous data strobe 71 2000
6,839,290 Method, apparatus, and system for high speed data transfer using source synchronous data strobe 67 2003
 
ROUND ROCK RESEARCH, LLC (66)
5,257,233 Low power memory module using restricted RAM activation 82 1990
5,278,796 Temperature-dependent DRAM refresh circuit 183 1991
5,282,177 Multiple register block write method and circuit for video DRAMs 101 1992
5,526,320 Burst EDO memory device 174 1994
5,610,864 Burst EDO memory device with maximized write cycle timing 119 1995
5,652,724 Burst EDO memory device having pipelined output buffer 117 1995
5,675,549 Burst EDO memory device address counter 107 1995
5,598,376 Distributed write data drivers for burst access memories 143 1995
5,729,503 Address transition detection on a synchronous design 101 1995
5,724,288 Data communication for memory 67 1995
5,668,773 Synchronous burst extended data out DRAM 100 1995
5,682,354 CAS recognition in burst extended data out DRAM 90 1995
5,721,859 Counter control circuit in a burst memory 98 1995
5,604,714 DRAM having multiple column address strobe operation 78 1995
5,640,364 Self-enabling pulse trapping circuit 105 1995
5,729,504 Continuous burst edo memory device 100 1995
5,627,791 Multiple bank memory with auto refresh to specified bank 224 1996
5,661,695 Burst EDO memory device 90 1996
5,802,010 Burst EDO memory device 80 1996
5,917,758 Adjustable output driver circuit 112 1996
5,703,813 DRAM having multiple column address strobe operation 74 1996
5,696,732 Burst EDO memory device 82 1996
5,706,247 Self-enabling pulse-trapping circuit 94 1996
5,949,254 Adjustable output driver circuit 146 1996
5,923,611 Memory having a plurality of external clock signal inputs 83 1996
5,838,177 Adjustable output driver circuit having parallel pull-up and pull-down elements 176 1997
5,757,703 Distributed write data drivers for burst access memories 88 1997
5,717,654 Burst EDO memory device with maximized write cycle timing 92 1997
5,812,488 Synchronous burst extended data out dram 82 1997
5,870,347 Multi-bank memory input/output line selection 128 1997
5,875,142 Integrated circuit with temperature detector 115 1997
5,831,931 Address strobe recognition in a memory device 70 1997
5,946,265 Continuous burst EDO memory device 95 1997
5,831,932 Self-enabling pulse-trapping circuit 74 1997
5,850,368 Burst EDO memory address counter 85 1997
6,002,613 Data communication for memory 67 1997
5,963,504 Address transition detection in a synchronous design 90 1997
6,016,282 Clock vernier adjustment 288 1998
6,069,504 Adjustable output driver circuit having parallel pull-up and pull-down elements 98 1998
6,029,250 Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same 402 1998
6,101,612 Apparatus for aligning clock and data signals received from a RAM 109 1998
6,108,795 Method for aligning clock and data signals received from a RAM 105 1998
6,044,032 Addressing scheme for a double data rate SDRAM 111 1998
6,002,627 Integrated circuit with temperature detector 101 1999
6,026,050 Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same 198 1999
6,326,810 Adjustable output driver circuit 76 1999
6,084,434 Adjustable output driver circuit 80 1999
6,453,402 Method for synchronizing strobe and data signals from a RAM 85 1999
6,307,769 Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices 86 1999
6,260,154 Apparatus for aligning clock and data signals received from a RAM 71 2000
6,330,683 Method for aligning clock and data signals received from a RAM 85 2000
6,356,500 Reduced power DRAM device and method 108 2000
6,496,440 Method and system for accessing rows in multiple memory banks within an integrated circuit 78 2001
6,801,989 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same 85 2001
6,437,600 Adjustable output driver circuit 75 2001
6,754,129 Memory module with integrated bus termination 70 2002
7,149,824 Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction 67 2002
7,120,727 Reconfigurable memory module and method 161 2003
7,428,644 System and method for selective memory module power management 82 2003
7,210,059 System and method for on-board diagnostics of memory modules 101 2003
6,862,202 Low power memory module using restricted device activation 59 2003
2006/0041,730 Memory command delay balancing in a daisy-chained memory topology 91 2004
7,046,538 Memory stacking system and method 83 2004
7,245,541 Active termination control 68 2005
7,269,042 Memory stacking system and method 88 2006
7,437,579 System and method for selective memory module power management 71 2006
 
EMC CORPORATION (2)
5,798,961 Non-volatile memory module 106 1994
5,742,792 Remote data mirroring 744 1996
 
INTEL CORPORATION (42)
5,388,265 Method and apparatus for placing an integrated circuit chip in a reduced power consumption state 193 1993
5,860,106 Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem 183 1995
5,692,202 System, apparatus, and method for managing power in a computer system 101 1995
6,279,069 Interface for flash EEPROM memory arrays 328 1996
5,884,088 System, apparatus and method for managing power in a computer system 102 1997
5,835,435 Method and apparatus for dynamically placing portions of a memory in a reduced power consumtion state 117 1997
6,298,426 Controller configurable for use with multiple memory organizations 115 1997
6,968,419 Memory module having a memory module controller controlling memory transactions for a plurality of memory devices 108 1998
6,970,968 Memory module controller for providing an interface between a system memory controller and a plurality of memory devices on a memory module 158 1998
6,233,650 Using FET switches for large memory arrays 149 1998
6,199,151 Apparatus and method for storing a device row indicator for use in a subsequent page-miss memory cycle 62 1998
6,587,912 Method and apparatus for implementing multiple memory buses on a memory module 304 1998
6,038,673 Computer system with power management scheme for DRAM devices 82 1998
6,442,698 Method and apparatus for power management in a memory subsystem 94 1998
6,457,095 Method and apparatus for synchronizing dynamic random access memory exiting from a low power state 77 1999
6,564,285 Synchronous interface for a nonvolatile memory 212 2000
6,356,105 Impedance control system for a center tapped termination bus 127 2000
6,317,352 Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules 331 2000
6,487,102 Memory module having buffer for isolating stacked memory devices 187 2000
* 6,553,450 Buffer to multiply memory interface 185 2000
6,820,163 Buffering data transfer between a chipset and memory modules 87 2000
6,862,653 System and method for controlling data flow direction in a memory system 65 2000
6,618,791 System and method for controlling power states of a memory device via detection of a chip select signal 101 2000
6,785,767 Hybrid mass storage system and method with two different types of storage medium 122 2000
6,563,337 Driver impedance control mechanism 76 2001
6,820,169 Memory control with lookahead power management 77 2001
2003/0105,932 Emulation of memory clock enable pin and use of chip select for memory power control 72 2001
6,714,891 Method and apparatus for thermal management of a power supply to a high performance processor in a computer system 96 2001
6,799,241 Method for dynamically adjusting a memory page closing policy 111 2002
7,024,518 Dual-port buffer-to-memory interface 94 2002
6,795,899 Memory system with burst length shorter than prefetch length 199 2002
7,103,730 Method, system, and apparatus for reducing power consumption of a memory 87 2002
6,639,820 Memory buffer arrangement 80 2002
6,747,887 Memory module having buffer for isolating stacked memory devices 84 2002
2005/0108,460 Partial bank DRAM refresh 77 2003
7,127,567 Performing memory RAS operations over a point-to-point interconnect 67 2003
2005/0138,267 Integral memory buffer and serial presence detect capability for fully-buffered memory modules 183 2003
7,085,152 Memory system segmented power supply and control 71 2003
7,133,960 Logical to physical address mapping of chip selects 102 2003
2005/0195,629 Interchangeable connection arrays for double-sided memory module placement 68 2004
2005/0204,111 Command scheduling for dual-data-rate two (DDR2) memory devices 65 2004
2006/0195,631 Memory buffers for merging local data from memory modules 131 2005
 
GENETICWARE CO., LTD. (1)
2003/0041,295 Method of defects recovery and status display of dram 76 2001
 
ALLERGAN, INC. (1)
5,453,434 N-substituted derivatives of 3R,4R-ethyl-[(1-methyl-1H-imidazol-5-yl)methyl]-2-pyrrolidone 56 1994
 
MITSUBISHI DENKI KABUSHIKI KAISHA (3)
4,794,597 Memory device equipped with a RAS circuit 95 1986
4,912,678 Dynamic random access memory device with staggered refresh 79 1988
5,384,745 Synchronous semiconductor memory device 296 1993
 
TAMIRAS PER PTE. LTD., LLC (2)
6,992,501 Reflection-control system and method 68 2004
7,033,861 Stacked module systems and method 64 2005
 
MICROSEMI SEMICONDUCTOR (U.S.) INC. (1)
6,047,073 Digital wavetable audio synthesizer with delay-based effects processing 111 1994
 
TOSHIBA STORAGE DEVICE CORPORATION (1)
6,324,120 Memory device having a variable data output length 70 2001
 
UT AUTOMOTIVE DEARBORN, INC. (1)
4,698,748 Power-conserving control system for turning-off the power and the clocking for data transactions upon certain system inactivity 397 1983
 
PROMOS TECHNOLOGIES INC. (1)
7,061,823 Limited output address register technique providing selectively variable write latency in DDR2 (double data rate two) integrated circuit memory devices 69 2004
 
DENSE-PAC MICROSYSTEMS, INC. (1)
2002/0089,831 Module with one side stacked memory 75 2001
 
ST. CLAIR INTELLECTUAL PROPERTY CONSULTANTS, INC. (1)
6,079,025 System and method of computer operating mode control for power consumption reduction 149 1998
 
APROLASE DEVELOPMENT CO., LLC (4)
4,706,166 High-density electronic modules--process and product 285 1986
4,983,533 High-density electronic modules - process and product 228 1987
5,104,820 Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting 267 1991
5,432,729 Electronic module comprising a stack of IC chips each interacting with an IC chip secured to the stack 313 1994
 
INTERNATIONAL MICROSYSTEMS, INC. (1)
6,473,831 Method and system for providing universal memory bus and module 82 1999
 
HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP (6)
6,073,223 Memory controller and method for intermittently activating and idling a clock signal for a synchronous memory 98 1997
6,389,514 Method and computer system for speculatively closing pages in memory 158 1999
6,684,292 Memory module resync 90 2001
6,665,227 Method and apparatus for reducing average power in RAMs by dynamically changing the bias on PFETs contained in memory cells 67 2001
7,028,215 Hot mirroring in a computer system with redundant memory subsystems 68 2002
2006/0236,165 Managing memory health 82 2005
 
ADVANTEST (SINGAPORE) PTE. LTD. (1)
5,654,204 Die sorter 175 1994
 
FREESCALE SEMICONDUCTOR, INC. (4)
4,935,734 Semi-conductor integrated circuits/systems 177 1986
4,780,843 Wait mode power reduction system and method for data processor 163 1987
5,467,455 Data processing system and method for performing dynamic bus termination 173 1993
5,929,650 Method and apparatus for performing operative testing on an integrated circuit 102 1997
 
High Connection Density, Inc. (2)
6,545,895 High capacity SDRAM memory module with stacked printed circuit boards 77 2002
6,705,877 Stackable memory module with variable bandwidth 97 2003
 
LENOVO INTERNATIONAL LIMITED (1)
2007/0106,860 REDISTRIBUTION OF MEMORY TO REDUCE COMPUTER SYSTEM POWER CONSUMPTION 99 2005
 
ELPIDA MEMORY, INC. (1)
5,332,922 Multi-chip semiconductor package 125 1991
 
TDK CORPORATION (13)
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 1 2003
 
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE (1)
5,924,111 Method and system for interleaving data in multiple memory bank partitions 107 1995
 
NEC CORPORATION (2)
5,831,833 Bear chip mounting printed circuit board and a method of manufacturing thereof by photoetching 98 1996
6,338,108 Coprocessor-integrated packet-type memory LSI, packet-type memory/coprocessor bus, and control method thereof 87 1998
 
AMIGA DEVELOPMENT LLC, A LIMITED LIABILITY COMPANY OF THE STATE OF DELAWARE (1)
4,710,903 Pseudo-static memory subsystem 90 1986
 
VERSYSS INCORPORATED, A DE CORP. (1)
4,796,232 Dual port memory controller 183 1987
 
MICROSOFT TECHNOLOGY LICENSING, LLC (8)
2003/0231,542 POWER GOVERNOR FOR DYNAMIC RAM 67 2002
2006/0090,031 Using external memory devices to improve system performance 82 2004
2006/0248,387 In-line non volatile memory disk read cache and write buffer 182 2005
2005/0235,119 Methods and mechanisms for proactive memory management 115 2005
7,093,101 Dynamic data structures for tracking file system free space in a flash memory device 112 2005
2007/0162,700 Optimizing write and wear performance for a memory 71 2005
2007/0288,683 Hybrid memory device with single interface 94 2006
2007/0288,687 High speed nonvolatile memory device 87 2006
 
Postech (1)
7,274,583 Memory system having multi-terminated multi-drop bus 68 2005
 
FUJITSU SEMICONDUCTOR LIMITED (1)
5,483,497 Semiconductor memory having a plurality of banks usable in a plurality of bank configurations 118 1994
 
ADVANTEST CORPORATION (1)
5,834,838 Pin array set-up device 79 1996
 
NEC ELECTRONICS CORPORATION (1)
4,841,440 Control processor for controlling a peripheral unit 174 1984
 
ELM 3DS INNOVATONS, LLC (1)
5,915,167 Three dimensional structure memory 691 1997
 
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. (3)
6,154,370 Recessed flip-chip package 88 1998
6,274,395 Method and apparatus for maintaining test data during fabrication of a semiconductor wafer 79 1999
6,807,655 Adaptive off tester screening method based on intrinsic die parametric measurements 82 2002
 
LAPIS SEMICONDUCTOR CO., LTD. (2)
6,510,097 DRAM interface circuit providing continuous access across row boundaries 75 2001
6,574,150 Dynamic random access memory with low power consumption 72 2002
 
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. (12)
6,134,638 Memory controller supporting DRAM circuits with different operating speeds 147 1997
6,510,503 High bandwidth memory interface 240 1998
RE36839 Method and apparatus for reducing power consumption in digital electronic circuits 115 1998
7,089,438 Circuit, system and method for selectively turning off internal clock drivers 77 2002
6,779,097 High bandwidth memory interface 73 2002
6,657,918 Delayed locked loop implementation in a synchronous dynamic random access memory 67 2002
6,657,919 Delayed locked loop implementation in a synchronous dynamic random access memory 69 2003
6,992,950 Delay locked loop implementation in a synchronous dynamic random access memory 66 2003
7,299,330 High bandwidth memory interface 65 2004
2005/0265,506 Delay locked loop implementation in a synchronous dynamic random access memory 64 2005
2008/0065,820 High bandwidth memory interface 65 2007
2008/0120,458 High bandwidth memory interface 70 2007
 
SMART MODULAR TECHNOLOGIES, INC. (1)
2008/0002,447 Memory supermodule utilizing point to point serial data links 66 2006
 
QUALCOMM INCORPORATED (1)
7,075,175 Systems and methods for testing packaged dies 90 2004
 
ERICSSON AB (1)
7,007,095 Method and apparatus for unscheduled flow control in packet form 67 2001
 
ALCATEL-LUCENT CANADA INC. (1)
2003/0123,389 Apparatus and method for controlling data transmission 140 2002
 
HITACHI TOHBU SEMICONDUCTOR, LTD. (1)
4,982,265 Semiconductor integrated circuit device and method of manufacturing the same 352 1988
 
THOMSON LICENSING (1)
2007/0091,696 Memory controller 64 2004
 
HONEYWELL INTERNATIONAL INC. (1)
6,765,812 Enhanced memory module architecture 94 2002
 
Honeywell Information Systems Inc. (1)
4,323,965 Sequential chip select decode apparatus and method 68 1980
 
DUX INC. (1)
5,966,727 Combination flash memory and dram memory board interleave-bypass memory access method, and memory access device incorporating both the same 128 1997
 
LONGITUDE SEMICONDUCTOR S.A.R.L. (2)
6,240,048 Synchronous type semiconductor memory system with less power consumption 93 2000
6,563,759 Semiconductor memory device 84 2001
 
ALCATEL (1)
6,908,314 Tailored interconnect module 65 2003
 
UNISYS CORPORATION (2)
5,761,703 Apparatus and method for dynamic memory refresh 72 1996
6,708,144 Spreadsheet driven I/O buffer synthesis process 85 1997
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (3)
6,455,348 Lead frame, resin-molded semiconductor device, and method for manufacturing the same 119 2000
6,674,154 Lead frame with multiple rows of external terminals 66 2002
6,710,430 Resin-encapsulated semiconductor device and method for manufacturing the same 67 2002
 
TALON RESEARCH, LLC (2)
5,347,428 Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip 290 1992
5,581,498 Stack of IC chips in lieu of single IC chip 329 1994
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
PATENTS1, LLC (1)
9,164,679 System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class 0 2015
 
INPHI CORPORATION (1)
9,123,441 Backward compatible dynamic random access memory device and method of testing therefor 0 2014
 
RAMBUS INC. (2)
* 8,537,601 Memory controller with selective data transmission delay 5 2012
* 2012/0287,725 MEMORY CONTROLLER WITH SELECTIVE DATA TRANSMISSION DELAY 1 2012
 
P4TENTS1, LLC (9)
8,930,647 Multiple class memory systems 20 2012
9,417,754 User interface system, method, and computer program product 0 2012
9,223,507 System, method and computer program product for fetching data between an execution of a plurality of threads 0 2015
9,195,395 Flash/DRAM/embedded DRAM-equipped system and method 0 2015
9,189,442 Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system 0 2015
9,182,914 System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class 0 2015
9,176,671 Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system 0 2015
9,170,744 Computer program product for controlling a flash/DRAM/embedded DRAM-equipped system 0 2015
9,158,546 Computer program product for fetching from a first physical memory between an execution of a plurality of threads associated with a second physical memory 0 2015
* Cited By Examiner

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
7.5 Year Payment $3600.00 $1800.00 $900.00 Jun 13, 2019
11.5 Year Payment $7400.00 $3700.00 $1850.00 Jun 13, 2023
Fee Large entity fee small entity fee micro entity fee
Surcharge - 7.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00