US Patent No: 8,077,535 - Analytics, PDF, Full Text and PAIR Access

Number of patents in Portfolio can not be more than 2000

Memory refresh apparatus and method

ALSO PUBLISHED AS: 20080025122

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A system and method are provided. The system and method simulate a DRAM memory circuit using an interface circuit connected to a plurality of other DRAM memory circuits. In response to the receipt of a refresh control signal, a first refresh control signal is sent to a first subset of the plurality of other DRAM memory circuits and a second refresh control signal is sent to a second subset of the plurality of other DRAM memory circuits.

Loading the Abstract Image... loading....

First Claim

See full text

all claims..

Related Publications

Loading Related Publications... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
GOOGLE INC.MOUNTAIN VIEW, CA10513

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rajan, Suresh Natarajan San Jose, CA 119 3112
Schakel, Keith R San Jose, CA 96 2917
Smith, Michael John Sebastian Palo Alto, CA 101 2891
Wang, David T San Jose, CA 137 3276
Weber, Frederick Daniel San Jose, CA 84 2685

Cited Art Landscape

Patent Info (Count) # Cites Year
 
ROUND ROCK RESEARCH, LLC (66)
5,257,233 Low power memory module using restricted RAM activation 76 1990
5,278,796 Temperature-dependent DRAM refresh circuit 166 1991
5,282,177 Multiple register block write method and circuit for video DRAMs 93 1992
5,526,320 Burst EDO memory device 166 1994
5,610,864 Burst EDO memory device with maximized write cycle timing 112 1995
5,652,724 Burst EDO memory device having pipelined output buffer 110 1995
5,675,549 Burst EDO memory device address counter 100 1995
5,598,376 Distributed write data drivers for burst access memories 135 1995
5,729,503 Address transition detection on a synchronous design 95 1995
5,724,288 Data communication for memory 61 1995
5,668,773 Synchronous burst extended data out DRAM 93 1995
5,682,354 CAS recognition in burst extended data out DRAM 84 1995
5,721,859 Counter control circuit in a burst memory 91 1995
5,604,714 DRAM having multiple column address strobe operation 72 1995
5,640,364 Self-enabling pulse trapping circuit 98 1995
5,729,504 Continuous burst edo memory device 93 1995
5,627,791 Multiple bank memory with auto refresh to specified bank 214 1996
5,661,695 Burst EDO memory device 83 1996
5,802,010 Burst EDO memory device 74 1996
5,917,758 Adjustable output driver circuit 104 1996
5,703,813 DRAM having multiple column address strobe operation 68 1996
5,696,732 Burst EDO memory device 76 1996
5,706,247 Self-enabling pulse-trapping circuit 84 1996
5,949,254 Adjustable output driver circuit 127 1996
5,923,611 Memory having a plurality of external clock signal inputs 77 1996
5,838,177 Adjustable output driver circuit having parallel pull-up and pull-down elements 155 1997
5,757,703 Distributed write data drivers for burst access memories 82 1997
5,717,654 Burst EDO memory device with maximized write cycle timing 86 1997
5,812,488 Synchronous burst extended data out dram 76 1997
5,870,347 Multi-bank memory input/output line selection 109 1997
5,875,142 Integrated circuit with temperature detector 103 1997
5,831,931 Address strobe recognition in a memory device 64 1997
5,946,265 Continuous burst EDO memory device 89 1997
5,831,932 Self-enabling pulse-trapping circuit 68 1997
5,850,368 Burst EDO memory address counter 78 1997
6,002,613 Data communication for memory 60 1997
5,963,504 Address transition detection in a synchronous design 84 1997
6,016,282 Clock vernier adjustment 258 1998
6,069,504 Adjustable output driver circuit having parallel pull-up and pull-down elements 91 1998
6,029,250 Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same 367 1998
6,101,612 Apparatus for aligning clock and data signals received from a RAM 99 1998
6,108,795 Method for aligning clock and data signals received from a RAM 96 1998
6,044,032 Addressing scheme for a double data rate SDRAM 102 1998
6,002,627 Integrated circuit with temperature detector 92 1999
6,026,050 Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same 176 1999
6,326,810 Adjustable output driver circuit 69 1999
6,084,434 Adjustable output driver circuit 73 1999
6,453,402 Method for synchronizing strobe and data signals from a RAM 77 1999
6,307,769 Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices 79 1999
6,260,154 Apparatus for aligning clock and data signals received from a RAM 65 2000
6,330,683 Method for aligning clock and data signals received from a RAM 75 2000
6,356,500 Reduced power DRAM device and method 101 2000
6,496,440 Method and system for accessing rows in multiple memory banks within an integrated circuit 70 2001
6,801,989 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same 75 2001
6,437,600 Adjustable output driver circuit 67 2001
6,754,129 Memory module with integrated bus termination 64 2002
7,149,824 Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction 58 2002
7,120,727 Reconfigurable memory module and method 145 2003
7,428,644 System and method for selective memory module power management 72 2003
7,210,059 System and method for on-board diagnostics of memory modules 94 2003
6,862,202 Low power memory module using restricted device activation 53 2003
2006/0041,730 Memory command delay balancing in a daisy-chained memory topology 76 2004
7,046,538 Memory stacking system and method 72 2004
7,245,541 Active termination control 62 2005
7,269,042 Memory stacking system and method 80 2006
7,437,579 System and method for selective memory module power management 62 2006
 
GOOGLE INC. (62)
5,519,832 Method and apparatus for displaying module diagnostic results 102 1995
6,618,267 Multi-level electronic package and method for making same 89 1998
7,515,453 Integrated memory core and memory interface circuit 59 2006
2007/0050,530 Integrated memory core and memory interface circuit 77 2006
7,580,312 Power saving system and method for use with a plurality of memory circuits 58 2006
7,609,567 System and method for simulating an aspect of a memory circuit 60 2006
7,724,589 System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits 54 2006
2008/0025,108 SYSTEM AND METHOD FOR DELAYING A SIGNAL COMMUNICATED FROM A SYSTEM TO AT LEAST ONE OF A PLURALITY OF MEMORY CIRCUITS 58 2006
2008/0025,122 MEMORY REFRESH SYSTEM AND METHOD 55 2006
2008/0025,136 SYSTEM AND METHOD FOR STORING AT LEAST A PORTION OF INFORMATION RECEIVED IN ASSOCIATION WITH A FIRST OPERATION FOR USE IN PERFORMING A SECOND OPERATION 58 2006
2008/0025,137 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 62 2006
2008/0027,702 SYSTEM AND METHOD FOR SIMULATING A DIFFERENT NUMBER OF MEMORY CIRCUITS 58 2006
2008/0028,135 MULTIPLE-COMPONENT MEMORY INTERFACE SYSTEM AND METHOD 61 2006
2008/0031,072 POWER SAVING SYSTEM AND METHOD FOR USE WITH A PLURALITY OF MEMORY CIRCUITS 53 2006
7,379,316 Methods and apparatus of stacking DRAMs 84 2006
2007/0058,471 Methods and apparatus of stacking DRAMs 69 2006
7,386,656 Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit 60 2006
7,392,338 Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits 57 2006
7,472,220 Interface circuit system and method for performing power management operations utilizing power management signals 58 2006
7,590,796 System and method for power management in memory systems 57 2006
2008/0031,030 System and method for power management in memory systems 74 2006
2008/0082,763 APPARATUS AND METHOD FOR POWER MANAGEMENT OF MEMORY CIRCUITS BY A SYSTEM OR COMPONENT THEREOF 57 2006
7,581,127 Interface circuit system and method for performing power saving operations during a command-related latency 54 2006
2008/0037,353 Interface circuit system and method for performing power saving operations during a command-related latency 53 2006
2008/0027,697 MEMORY CIRCUIT SIMULATION SYSTEM AND METHOD WITH POWER SAVING CAPABILITIES 55 2006
2008/0027,703 MEMORY CIRCUIT SIMULATION SYSTEM AND METHOD WITH REFRESH CAPABILITIES 54 2006
2008/0123,459 COMBINED SIGNAL DELAY AND POWER SAVING SYSTEM AND METHOD FOR USE WITH A PLURALITY OF MEMORY CIRCUITS 55 2006
2008/0086,588 System and Method for Increasing Capacity, Performance, and Flexibility of Flash Storage 64 2006
2007/0195,613 Memory module with memory stack and interface with enhanced capabilities 76 2007
2008/0126,690 Memory module with memory stack 79 2007
2007/0192,563 SYSTEM AND METHOD FOR TRANSLATING AN ADDRESS ASSOCIATED WITH A COMMAND COMMUNICATED BETWEEN A SYSTEM AND MEMORY CIRCUITS 66 2007
2007/0204,075 SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS 65 2007
2008/0056,014 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 59 2007
2008/0062,773 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 58 2007
2008/0010,435 MEMORY SYSTEMS AND MEMORY MODULES 81 2007
2008/0028,136 METHOD AND APPARATUS FOR REFRESH MANAGEMENT OF MEMORY MODULES 55 2007
2008/0028,137 Method and Apparatus For Refresh Management of Memory Modules 60 2007
2008/0103,753 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 63 2007
2008/0104,314 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 59 2007
2008/0109,206 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 59 2007
2008/0109,595 SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS 63 2007
2008/0109,597 METHOD AND APPARATUS FOR REFRESH MANAGEMENT OF MEMORY MODULES 59 2007
2008/0109,598 Method and apparatus for refresh management of memory modules 60 2007
2008/0120,443 SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS 61 2007
2008/0126,687 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 59 2007
2008/0126,688 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 59 2007
2008/0126,689 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 59 2007
2008/0126,692 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 60 2007
2008/0133,825 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 59 2007
2009/0024,789 MEMORY CIRCUIT SYSTEM AND METHOD 71 2007
2009/0024,790 MEMORY CIRCUIT SYSTEM AND METHOD 59 2007
2008/0115,006 SYSTEM AND METHOD FOR ADJUSTING THE TIMING OF SIGNALS ASSOCIATED WITH A MEMORY SYSTEM 70 2007
7,599,205 Methods and apparatus of stacking DRAMs 61 2008
2008/0170,425 METHODS AND APPARATUS OF STACKING DRAMS 78 2008
7,730,338 Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits 56 2008
7,761,724 Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit 54 2008
2008/0239,857 INTERFACE CIRCUIT SYSTEM AND METHOD FOR PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH ONLY A PORTION OF A MEMORY CIRCUIT 54 2008
2008/0239,858 INTERFACE CIRCUIT SYSTEM AND METHOD FOR AUTONOMOUSLY PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH A PLURALITY OF MEMORY CIRCUITS 54 2008
2009/0216,939 Emulation of abstracted DIMMs using abstracted DRAMs 55 2009
2009/0285,031 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 55 2009
2009/0290,442 METHOD AND CIRCUIT FOR CONFIGURING MEMORY CORE INTEGRATED CIRCUIT DIES WITH MEMORY INTERFACE INTEGRATED CIRCUIT DIES 55 2009
2010/0020,585 METHODS AND APPARATUS OF STACKING DRAMS 55 2009
 
INTEL CORPORATION (44)
5,388,265 Method and apparatus for placing an integrated circuit chip in a reduced power consumption state 183 1993
5,860,106 Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem 165 1995
5,692,202 System, apparatus, and method for managing power in a computer system 90 1995
6,279,069 Interface for flash EEPROM memory arrays 282 1996
5,884,088 System, apparatus and method for managing power in a computer system 93 1997
5,835,435 Method and apparatus for dynamically placing portions of a memory in a reduced power consumtion state 105 1997
6,298,426 Controller configurable for use with multiple memory organizations 102 1997
6,968,419 Memory module having a memory module controller controlling memory transactions for a plurality of memory devices 99 1998
6,970,968 Memory module controller for providing an interface between a system memory controller and a plurality of memory devices on a memory module 136 1998
6,233,650 Using FET switches for large memory arrays 138 1998
6,199,151 Apparatus and method for storing a device row indicator for use in a subsequent page-miss memory cycle 55 1998
6,587,912 Method and apparatus for implementing multiple memory buses on a memory module 290 1998
6,038,673 Computer system with power management scheme for DRAM devices 76 1998
6,442,698 Method and apparatus for power management in a memory subsystem 86 1998
6,457,095 Method and apparatus for synchronizing dynamic random access memory exiting from a low power state 68 1999
6,621,760 Method, apparatus, and system for high speed data transfer using source synchronous data strobe 65 2000
6,564,285 Synchronous interface for a nonvolatile memory 126 2000
6,356,105 Impedance control system for a center tapped termination bus 100 2000
6,317,352 Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules 305 2000
6,487,102 Memory module having buffer for isolating stacked memory devices 166 2000
6,553,450 Buffer to multiply memory interface 173 2000
6,820,163 Buffering data transfer between a chipset and memory modules 79 2000
6,862,653 System and method for controlling data flow direction in a memory system 59 2000
6,618,791 System and method for controlling power states of a memory device via detection of a chip select signal 84 2000
6,785,767 Hybrid mass storage system and method with two different types of storage medium 99 2000
6,563,337 Driver impedance control mechanism 70 2001
6,820,169 Memory control with lookahead power management 69 2001
2003/0105,932 Emulation of memory clock enable pin and use of chip select for memory power control 65 2001
6,714,891 Method and apparatus for thermal management of a power supply to a high performance processor in a computer system 81 2001
6,799,241 Method for dynamically adjusting a memory page closing policy 96 2002
7,024,518 Dual-port buffer-to-memory interface 82 2002
6,795,899 Memory system with burst length shorter than prefetch length 186 2002
7,103,730 Method, system, and apparatus for reducing power consumption of a memory 79 2002
6,639,820 Memory buffer arrangement 71 2002
6,747,887 Memory module having buffer for isolating stacked memory devices 74 2002
6,839,290 Method, apparatus, and system for high speed data transfer using source synchronous data strobe 60 2003
2005/0108,460 Partial bank DRAM refresh 67 2003
7,127,567 Performing memory RAS operations over a point-to-point interconnect 58 2003
2005/0138,267 Integral memory buffer and serial presence detect capability for fully-buffered memory modules 169 2003
7,085,152 Memory system segmented power supply and control 64 2003
7,133,960 Logical to physical address mapping of chip selects 86 2003
2005/0195,629 Interchangeable connection arrays for double-sided memory module placement 60 2004
2005/0204,111 Command scheduling for dual-data-rate two (DDR2) memory devices 58 2004
2006/0195,631 Memory buffers for merging local data from memory modules 117 2005
 
RAMBUS INC. (44)
5,748,914 Protocol for communication with dynamic memory 132 1995
5,841,580 Integrated circuit I/O using a high performance bus interface 89 1997
5,954,804 Synchronous memory device having an internal register 134 1997
5,915,105 Integrated circuit I/O using a high performance bus interface 123 1997
6,075,730 High performance cost optimized memory with delayed memory writes 124 1998
6,075,744 Dram core refresh with reduced spike current 68 1998
5,953,263 Synchronous memory device having a programmable register and method of controlling same 116 1998
6,038,195 Synchronous memory device having a delay time register and method of operating same 101 1998
6,035,365 Dual clocked synchronous memory device having a delay time register and method of operating same 93 1998
6,101,152 Method of operating a synchronous memory device 140 1998
6,032,214 Method of operating a synchronous memory device having a variable data output length 99 1999
6,034,918 Method of operating a memory having a variable data output length and a programmable register 96 1999
5,995,443 Synchronous memory device 100 1999
6,032,215 Synchronous memory device utilizing two external clocks 58 1999
6,452,863 Method of operating a memory device having a variable data input length 60 2000
6,182,184 Method of operating a memory device having a variable data input length 65 2000
6,260,097 Method and apparatus for controlling a synchronous memory device 100 2000
6,378,020 System having double data transfer rate and intergrated circuit therefor 68 2000
6,266,292 DRAM core refresh with reduced spike current 61 2000
6,343,042 DRAM core refresh with reduced spike current 59 2000
6,266,285 Method of operating a memory device having write latency 104 2000
6,314,051 Memory device having write latency 112 2000
6,426,916 Memory device having a variable data output length and a programmable register 68 2001
6,697,295 Memory device having a programmable register 60 2001
6,751,696 Memory device having a programmable register 63 2001
6,496,897 Semiconductor memory device which receives write masking information 109 2001
6,701,446 Power control system for synchronous memory device 101 2001
6,493,789 Memory device which receives write masking and automatic precharge information 111 2001
6,564,281 Synchronous memory device having automatic precharge 61 2001
6,546,446 Synchronous memory device having automatic precharge 57 2001
6,807,598 Integrated circuit device having double data rate capability 64 2002
6,597,616 DRAM core refresh with reduced spike current 56 2002
6,584,037 Memory device which samples data after an amount of time transpires 90 2002
7,043,599 Dynamic memory supporting simultaneous refresh and data-access transactions 103 2002
7,363,422 Configurable width buffered module 67 2004
7,269,708 Memory controller for non-homogenous memory system 77 2004
7,003,639 Memory controller with power management logic 69 2004
7,010,642 System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices 71 2004
7,000,062 System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices 102 2005
7,003,618 System featuring memory modules that include an integrated circuit buffer devices 61 2005
7,581,121 System for a memory device having a power down mode and method 54 2005
7,464,225 Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology 67 2005
2007/0279,084 INTEGRATED CIRCUIT WITH GRADUATED ON-DIE TERMINATION 52 2006
2007/0088,995 SYSTEM INCLUDING A BUFFERED MEMORY MODULE 82 2006
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (29)
4,862,347 System for simulating memory arrays in a logic simulation machine 125 1986
4,884,237 Stacked double density memory module using industry standard memory chips 177 1989
4,922,451 Memory re-mapping in a microcomputer system 66 1989
5,502,667 Integrated multichip memory module structure 162 1993
5,561,622 Integrated memory cube structure 158 1993
5,502,333 Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit 207 1994
5,530,836 Method and apparatus for multiple memory bank selection 66 1994
5,513,135 Synchronous memory packaged in single/dual in-line memory module and method of fabrication 341 1994
5,563,086 Integrated memory cube, structure and fabrication 116 1995
5,872,907 Fault tolerant design for identification of AC defects including variance of cycle time to maintain system operation 75 1995
5,590,071 Method and apparatus for emulating a high capacity DRAM 84 1995
5,680,342 Memory module package with address bus buffering 65 1996
5,692,121 Recovery unit for mirrored processors 82 1996
5,802,395 High density memory modules with improved data bus performance 128 1996
5,702,984 Integrated mulitchip memory module, structure and fabrication 110 1996
5,870,350 High performance, high bandwidth memory bus architecture utilizing SDRAMs 176 1997
5,943,254 Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes 109 1997
5,963,464 Stackable memory card 122 1998
6,070,217 High density memory module with in-line bus switches being enabled in response to read/write selection state of connected RAM banks to improve data bus performance 100 1998
6,327,664 Power management on a memory card having a signal processing element 66 1999
6,453,434 Dynamically-tunable memory controller 64 2001
6,490,161 Peripheral land grid array package with improved thermal performance 99 2002
6,968,416 Method, system, and program for processing transaction requests during a pendency of a delayed read request in a system including a bus, a target device and devices capable of accessing the target device over the bus 62 2002
7,480,774 Method for performing a command cancel function in a DRAM 58 2003
7,224,595 276-Pin buffered memory module with enhanced fault tolerance 115 2004
7,539,800 System, method and storage medium for providing segment level sparing 61 2004
2007/0106,860 REDISTRIBUTION OF MEMORY TO REDUCE COMPUTER SYSTEM POWER CONSUMPTION 84 2005
7,366,947 High reliability memory module with a fault tolerant address and command bus 59 2006
2008/0098,277 HIGH DENSITY HIGH RELIABILITY MEMORY MODULE WITH POWER GATING AND A FAULT TOLERANT ADDRESS AND COMMAND BUS 80 2006
 
MICRON TECHNOLOGY, INC. (23)
4,899,107 Discrete die burn-in for nonpackaged die 218 1988
5,241,266 Built-in test circuit connection for wafer level burnin and testing of individual dies 140 1992
5,408,190 Testing apparatus having substrate interconnect for discrete die burn-in for nonpackaged die 197 1993
5,907,512 Mask write enablement for memory devices which permits selective masked enablement of plural segments 69 1993
5,966,724 Synchronous memory device with dual page and burst mode operations 255 1996
5,661,677 Circuit and method for on-board programming of PRD Serial EEPROMS 128 1996
5,903,500 1.8 volt output buffer on flash memories 69 1997
5,901,105 Dynamic random access memory having decoding circuitry for partial memory blocks 111 1997
5,859,792 Circuit for on-board programming of PRD serial EEPROMs 69 1997
5,963,463 Method for on-board programming of PRD serial EEPROMS 73 1997
6,111,812 Method and apparatus for adjusting control signal timing in a memory device 90 1999
6,317,381 Method and system for adaptively adjusting control signal timing in a memory device 74 1999
6,304,511 Method and apparatus for adjusting control signal timing in a memory device 70 2000
6,243,282 Apparatus for on-board programming of serial EEPROMs 64 2000
6,731,527 Architecture for a semiconductor memory device for minimizing interference and cross-coupling between control signal lines and power lines 60 2001
6,912,778 Methods of fabricating full-wafer silicon probe cards for burn-in and testing of semiconductor devices 65 2001
6,418,034 Stacked printed circuit board memory module and method of augmenting memory therein 64 2001
6,771,526 Method and apparatus for data transfer 65 2002
6,847,582 Low skew clock input buffer and method 81 2003
2006/0010,339 Memory system and method having selective ECC during low power refresh 94 2004
7,149,145 Delay stage-interweaved analog DLL/PLL 60 2004
6,947,341 Integrated semiconductor memory chip with presence detect data capability 59 2004
7,573,136 Semiconductor device assemblies and packages including multiple semiconductor device components 57 2005
 
SAMSUNG ELECTRONICS CO., LTD. (23)
5,845,108 Semiconductor memory device using asynchronous signal 91 1996
6,078,546 Synchronous semiconductor memory device with double data rate scheme 111 1998
6,208,168 Output driver circuits having programmable pull-up and pull-down capability for driving variable loads 71 1998
6,034,916 Data masking circuits and methods for integrated circuit memory devices, including data strobe signal synchronization 95 1998
6,526,473 Memory module system for controlling data input and output by connecting selected memory modules to a data line 77 1999
6,381,188 DRAM capable of selectively performing self-refresh operation for memory bank 78 2000
6,262,938 Synchronous DRAM having posted CAS latency and method for controlling CAS latency 83 2000
6,362,656 Integrated circuit memory devices having programmable output driver circuits therein 71 2001
6,452,826 Memory module system 116 2001
6,498,766 Integrated circuit memory devices that utilize indication signals to increase reliability of reading and writing operations and methods of operating same 83 2001
6,459,651 Semiconductor memory device having data masking pin and memory system including the same 66 2001
6,590,822 System and method for performing partial array self-refresh operation in a semiconductor memory device 90 2001
6,560,158 Power down voltage control method and apparatus 70 2001
6,754,132 Devices and methods for controlling active termination resistors in a memory system 74 2002
6,762,948 Semiconductor memory device having first and second memory architecture and memory system using the same 67 2002
6,819,602 Multimode data buffer and method for controlling propagation delay time 72 2002
6,650,594 Device and method for selecting power down exit 89 2002
7,058,776 Asynchronous memory using source synchronous transfer and system employing the same 70 2003
6,819,617 System and method for performing partial array self-refresh operation in a semiconductor memory device 69 2003
7,215,561 Semiconductor memory system having multiple system data buses 62 2003
6,862,249 Devices and methods for controlling active termination resistors in a memory system 58 2004
2004/0196,732 Multi-stage output multiplexing circuits and methods for double data rate synchronous memory devices 61 2004
2005/0224,948 Semiconductor device package having buffered memory module and method thereof 55 2005
 
RENESAS ELECTRONICS CORPORATION (13)
5,220,672 Low power consuming digital circuit device 94 1991
6,453,400 Semiconductor integrated circuit device 65 1998
6,252,807 Memory device with reduced power consumption when byte-unit accessed 53 1999
2002/0129,298 Method of and apparatus for testing CPU built-in RAM mixed LSI 2001
6,922,371 Semiconductor storage device 61 2002
6,791,877 Semiconductor device with non-volatile memory and random access memory 96 2002
6,597,617 Semiconductor device with reduced current consumption in standby state 62 2002
6,650,588 Semiconductor memory module and register buffer device for use in the same 66 2002
7,136,978 System and method for using dynamic random access memory and flash memory 64 2003
6,850,449 Semiconductor memory device having mode storing one bit data in two memory cells and method of controlling same 72 2003
7,613,880 Memory module, memory system, and information device 63 2003
2006/0041,711 Memory module, memory system, and information device 72 2003
7,296,754 IC card module 68 2005
 
TDK CORPORATION (13)
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
2004/0100,736 Head support mechanism and thin film piezoelectric actuator 2003
 
QIMONDA AG (12)
6,526,484 Methods and apparatus for reordering of the memory requests to achieve higher average utilization of the command and data bus 77 1999
6,438,057 DRAM refresh timing adjustment device, system and method 124 2001
6,614,700 Circuit configuration with a memory array 57 2002
7,028,234 Method of self-repairing dynamic random access memory 59 2002
7,035,150 Memory device with column select being variably delayed 63 2002
6,986,118 Method for controlling semiconductor chips and control apparatus 61 2003
7,231,562 Memory module, test system and method for testing one or a plurality of memory modules 124 2004
6,894,933 Buffer amplifier architecture for semiconductor memory circuits 64 2004
7,061,784 Semiconductor memory module 61 2004
7,200,021 Stacked DRAM memory chip for a dual inline memory module (DIMM) 110 2004
7,266,639 Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM) 80 2004
7,079,441 Methods and apparatus for implementing a power down in a memory device 62 2005
 
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. (11)
6,510,503 High bandwidth memory interface 210 1998
RE36839 Method and apparatus for reducing power consumption in digital electronic circuits 101 1998
7,089,438 Circuit, system and method for selectively turning off internal clock drivers 68 2002
6,779,097 High bandwidth memory interface 67 2002
6,657,918 Delayed locked loop implementation in a synchronous dynamic random access memory 61 2002
6,657,919 Delayed locked loop implementation in a synchronous dynamic random access memory 63 2003
6,992,950 Delay locked loop implementation in a synchronous dynamic random access memory 59 2003
7,299,330 High bandwidth memory interface 58 2004
2005/0265,506 Delay locked loop implementation in a synchronous dynamic random access memory 57 2005
2008/0065,820 High bandwidth memory interface 57 2007
2008/0120,458 High bandwidth memory interface 63 2007
 
Netlist, Inc. (11)
6,751,113 Arrangement of integrated circuits in a memory module 163 2002
6,930,900 Arrangement of integrated circuits in a memory module 56 2004
6,930,903 Arrangement of integrated circuits in a memory module 58 2004
2005/0018,495 ARRANGEMENT OF INTEGRATED CIRCUITS IN A MEMORY MODULE 101 2004
6,873,534 Arrangement of integrated circuits in a memory module 86 2004
7,286,436 High-density memory module utilizing low-density memory components 74 2005
7,254,036 High density memory module using stacked printed circuit boards 66 2005
7,289,386 Memory module decoder 86 2005
7,532,537 Memory module with a circuit providing load isolation and memory domain translation 84 2006
2006/0262,586 Memory module with a circuit providing load isolation and memory domain translation 73 2006
7,619,912 Memory module decoder 72 2007
 
SUN MICROSYSTEMS, INC. (10)
6,341,347 Thread switch logic in a multiple-thread processor 175 1999
6,414,868 Memory expansion module including multiple memory banks and a bank control circuit 110 1999
6,683,372 Memory expansion module with stacked memory packages and a serial storage unit 111 1999
6,658,530 High-performance memory module 65 2000
6,816,991 Built-in self-testing for double data rate input/output 79 2001
6,690,191 Bi-directional output buffer 78 2001
6,938,119 DRAM power management 125 2002
6,961,281 Single rank memory module for use in a two-rank memory module system 107 2003
2006/0112,219 Functional partitioning method for providing modular data storage systems 94 2004
7,496,777 Power throttling in a memory system 67 2005
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (9)
6,073,223 Memory controller and method for intermittently activating and idling a clock signal for a synchronous memory 90 1997
6,134,638 Memory controller supporting DRAM circuits with different operating speeds 130 1997
6,389,514 Method and computer system for speculatively closing pages in memory 143 1999
6,766,469 Hot-replace of memory 87 2001
6,684,292 Memory module resync 80 2001
6,665,227 Method and apparatus for reducing average power in RAMs by dynamically changing the bias on PFETs contained in memory cells 61 2001
7,028,215 Hot mirroring in a computer system with redundant memory subsystems 60 2002
7,234,081 Memory module with testing logic 59 2004
2006/0236,165 Managing memory health 68 2005
 
MICROSOFT CORPORATION (8)
2003/0231,542 POWER GOVERNOR FOR DYNAMIC RAM 61 2002
2006/0090,031 Using external memory devices to improve system performance 66 2004
2006/0248,387 In-line non volatile memory disk read cache and write buffer 115 2005
2005/0235,119 Methods and mechanisms for proactive memory management 85 2005
7,093,101 Dynamic data structures for tracking file system free space in a flash memory device 82 2005
2007/0162,700 Optimizing write and wear performance for a memory 59 2005
2007/0288,683 Hybrid memory device with single interface 71 2006
2007/0288,687 High speed nonvolatile memory device 68 2006
 
FUJITSU SEMICONDUCTOR LIMITED (7)
5,483,497 Semiconductor memory having a plurality of banks usable in a plurality of bank configurations 108 1994
6,014,339 Synchronous DRAM whose power consumption is minimized 93 1997
6,353,561 Semiconductor integrated circuit and method for controlling the same 62 1999
6,594,770 Semiconductor integrated circuit device 66 1999
6,898,683 Clock synchronized dynamic memory and clock synchronized integrated circuit 67 2001
7,302,598 Apparatus to reduce the internal frequency of an integrated circuit by detecting a drop in the voltage and frequency 62 2004
6,845,055 Semiconductor memory capable of transitioning from a power-down state in a synchronous mode to a standby state in an asynchronous mode without setting by a control register 69 2004
 
KABUSHIKI KAISHA TOSHIBA (6)
5,083,266 Microcomputer which enters sleep mode for a predetermined period of time on response to an activity of an input/output device 269 1987
6,047,344 Semiconductor memory device with multiplied internal clock 62 1998
6,088,290 Semiconductor memory device having a power-down mode 80 1998
2002/0089,970 Multimedia private branch exchanger and private branch exchange system 57 2002
7,058,863 Semiconductor integrated circuit 66 2002
6,826,104 Synchronous semiconductor memory 62 2002
 
NATIONAL SEMICONDUCTOR CORPORATION (6)
4,887,240 Staggered refresh for dram array 64 1987
5,606,710 Multiple chip package processor having feed through paths on one die 70 1994
5,566,344 In-system programming architecture for a multiple chip processor 70 1995
5,581,779 Multiple chip processor architecture with memory interface control register for in-system programming 64 1995
5,623,686 Non-volatile memory control and data loading architecture for multiple chip processor 63 1995
5,781,766 Programmable compensating device to optimize performance in a DRAM controller chipset 79 1996
 
INFINEON TECHNOLOGIES AG (5)
7,228,264 Program-controlled unit 57 2002
6,665,224 Partial refresh for synchronous dynamic random access memory (SDRAM) circuits 66 2002
2006/0129,712 Buffer chip for a multi-rank dual inline memory module (DIMM) 63 2004
2006/0129,740 Memory device, memory controller and method for operating the same 50 2004
2006/0294,295 DRAM chip device well-communicated with flash memory chip and multi-chip package comprising such a device 84 2005
 
INPHI CORPORATION (5)
6,980,021 Output buffer with time varying source impedance for driving capacitively-terminated transmission lines 74 2004
7,307,863 Programmable strength output buffer for RDIMM address register 67 2005
2007/0216,445 Output buffer with switchable output impedance 57 2006
2007/0247,194 Output buffer to drive AC-coupled terminated transmission lines 58 2006
7,408,393 Master-slave flip-flop and clocking scheme 58 2007
 
APROLASE DEVELOPMENT CO., LLC (4)
4,706,166 High-density electronic modules--process and product 270 1986
4,983,533 High-density electronic modules - process and product 218 1987
5,104,820 Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting 260 1991
5,432,729 Electronic module comprising a stack of IC chips each interacting with an IC chip secured to the stack 275 1994
 
FREESCALE SEMICONDUCTOR, INC. (4)
4,935,734 Semi-conductor integrated circuits/systems 170 1986
4,780,843 Wait mode power reduction system and method for data processor 156 1987
5,467,455 Data processing system and method for performing dynamic bus termination 132 1993
5,929,650 Method and apparatus for performing operative testing on an integrated circuit 95 1997
 
HYNIX SEMICONDUCTOR INC. (4)
6,646,939 Low power type Rambus DRAM 59 2002
6,724,684 Apparatus for pipe latch control circuit in synchronous memory device 70 2002
6,744,687 Semiconductor memory device with mode register and method for controlling deep power down mode therein 82 2002
2008/0159,027 SEMICONDUCTOR MEMORY DEVICE WITH MIRROR FUNCTION MODULE AND USING THE SAME 56 2007
 
OVID DATA CO. LLC (4)
5,843,807 Method of manufacturing an ultra-high density warp-resistant memory module 72 1996
7,026,708 Low profile chip scale stacking system and method 58 2003
6,992,501 Reflection-control system and method 62 2004
7,033,861 Stacked module systems and method 57 2005
 
VIA TECHNOLOGIES, INC. (4)
2001/0003,198 Method for timing setting of a system memory 86 2000
7,007,175 Motherboard with reduced power consumption 86 2001
2005/0289,317 METHOD AND RELATED APPARATUS FOR ACCESSING MEMORY 86 2005
7,441,064 Flexible width data protocol 48 2006
 
EMC CORPORATION (3)
5,798,961 Non-volatile memory module 97 1994
5,742,792 Remote data mirroring 636 1996
6,058,451 Method and apparatus for refreshing a non-clocked memory 63 1997
 
FUJITSU LIMITED (3)
4,392,212 Semiconductor memory device with decoder for chip selection/write in 80 1980
6,664,625 Mounting structure of a semiconductor device 55 2002
7,085,941 Clock control apparatus and method, for a memory controller, that processes a block access into single continuous macro access while minimizing power consumption 63 2003
 
HITACHI, LTD. (3)
6,430,103 Semiconductor integrated circuit device with memory banks and read buffer capable of storing data read out from one memory bank when data of another memory bank is outputting 73 2001
7,119,428 Semiconductor device 70 2004
7,409,492 Storage system using flash memory modules logically grouped for wear-leveling and RAID 104 2006
 
IRVINE SENSORS CORPORATION (3)
4,525,921 High-density electronic processing package-structure and fabrication 207 1983
4,646,128 High-density electronic processing package--structure and fabrication 150 1985
4,764,846 High density electronic package comprising stacked sub-modules 219 1987
 
LSI LOGIC CORPORATION (3)
5,640,337 Method and apparatus for interim in-situ testing of an electronic system with an inchoate ASIC 77 1996
6,274,395 Method and apparatus for maintaining test data during fabrication of a semiconductor wafer 73 1999
6,807,655 Adaptive off tester screening method based on intrinsic die parametric measurements 74 2002
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (3)
6,455,348 Lead frame, resin-molded semiconductor device, and method for manufacturing the same 98 2000
6,674,154 Lead frame with multiple rows of external terminals 59 2002
6,710,430 Resin-encapsulated semiconductor device and method for manufacturing the same 59 2002
 
MITSUBISHI DENKI KABUSHIKI KAISHA (3)
4,794,597 Memory device equipped with a RAS circuit 88 1986
4,912,678 Dynamic random access memory device with staggered refresh 72 1988
5,384,745 Synchronous semiconductor memory device 278 1993
 
NEC CORPORATION (3)
5,831,833 Bear chip mounting printed circuit board and a method of manufacturing thereof by photoetching 89 1996
5,973,392 Stacked carrier three-dimensional memory module and semiconductor device using the same 85 1998
6,338,108 Coprocessor-integrated packet-type memory LSI, packet-type memory/coprocessor bus, and control method thereof 78 1998
 
PS4 LUXCO S.A.R.L. (3)
5,969,996 Semiconductor memory device and memory system 64 1998
6,240,048 Synchronous type semiconductor memory system with less power consumption 82 2000
6,563,759 Semiconductor memory device 74 2001
 
SPANSION LLC (3)
6,480,929 Pseudo-concurrency between a volatile memory and a non-volatile memory on a same data bus 79 1998
6,631,086 On-chip repair of defective address of core flash memory cells 76 2002
7,010,736 Address sequencer within BIST (Built-in-Self-Test) system 68 2002
 
TEXAS INSTRUMENTS INCORPORATED (3)
6,421,754 System management mode circuits, systems and methods 119 1995
5,802,555 Computer system including a refresh controller circuit having a row address strobe multiplexer and associated method 112 1997
5,956,233 High density single inline memory module 89 1997
 
ADVANTEST (SINGAPORE) PTE LTD (2)
5,654,204 Die sorter 168 1994
5,834,838 Pin array set-up device 72 1996
 
CYPRESS SEMICONDUCTOR CORPORATION (2)
6,166,991 Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit 62 1999
6,363,031 Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit 62 2000
 
HIGH CONNECTION DENSITY, INC. (2)
6,545,895 High capacity SDRAM memory module with stacked printed circuit boards 68 2002
6,705,877 Stackable memory module with variable bandwidth 83 2003
 
Honeywell Information Systems Inc. (2)
4,334,307 Data processing system with self testing and configuration mapping capability 142 1979
4,323,965 Sequential chip select decode apparatus and method 61 1980
 
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. (2)
5,926,435 Apparatus for saving power consumption in semiconductor memory devices 63 1997
6,772,359 Clock control circuit for Rambus DRAM 59 2000
 
KINGSTON TECHNOLOGY CORPORATION (2)
7,317,250 High density memory card assembly 54 2004
7,474,576 Repairing Advanced-Memory Buffer (AMB) with redundant memory buffer for repairing DRAM on a fully-buffered memory-module 58 2008
 
LAPIS SEMICONDUCTOR CO., LTD. (2)
6,510,097 DRAM interface circuit providing continuous access across row boundaries 67 2001
6,574,150 Dynamic random access memory with low power consumption 66 2002
 
MOSYS, INC. (2)
5,498,886 Circuit module redundancy architecture 81 1994
5,843,799 Circuit module redundancy architecture process 90 1997
 
TALON RESEARCH, LLC (2)
5,347,428 Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip 265 1992
5,581,498 Stack of IC chips in lieu of single IC chip 291 1994
 
UNISYS CORPORATION (2)
5,761,703 Apparatus and method for dynamic memory refresh 65 1996
6,708,144 Spreadsheet driven I/O buffer synthesis process 78 1997
 
URENSCHI ASSETS LIMITED LIABILITY COMPANY (2)
5,953,215 Apparatus and method for improving computer memory speed and capacity 182 1998
7,205,789 Termination arrangement for high speed data rate multi-drop data bit connections 57 2005
 
Advanced Interconnect Solutions (1)
2002/0015,340 Method and apparatus for memory module circuit interconnection 60 2001
 
ADVANCED MICRO DEVICES, INC. (1)
5,559,990 Memories with burst mode access 91 1994
 
AGERE SYSTEMS INC. (1)
6,154,370 Recessed flip-chip package 81 1998
 
AGILENT TECHNOLOGIES, INC. (1)
5,025,364 Microprocessor emulation system with memory mapping using variable definition and addressing of memory space 65 1987
 
ALCATEL (1)
6,908,314 Tailored interconnect module 59 2003
 
ALCATEL-LUCENT CANADA INC. (1)
2003/0123,389 Apparatus and method for controlling data transmission 114 2002
 
ALLERGAN, INC. (1)
5,453,434 N-substituted derivatives of 3R,4R-ethyl-[(1-methyl-1H-imidazol-5-yl)methyl]-2-pyrrolidone 51 1994
 
AMETEK, INC., COMPUTER RESEARCH DIVISION (1)
4,937,791 High performance dynamic ram interface 88 1988
 
AMIGA DEVELOPMENT LLC, A LIMITED LIABILITY COMPANY OF THE STATE OF DELAWARE (1)
4,710,903 Pseudo-static memory subsystem 84 1986
 
Anamartic Limited (1)
5,072,424 Wafer-scale integrated circuit memory 61 1987
 
ARRIS ENTERPRISES, INC. (1)
6,526,471 Method and apparatus for a high-speed memory subsystem 72 1998
 
AT&T IPM CORP. (1)
5,513,339 Concurrent fault simulation of circuits with both logic elements and functional circuits 142 1994
 
Bell Telephone Laboratories, Incorporated (1)
4,592,019 Bus oriented LIFO/FIFO memory 82 1983
 
BITMICRO NETWORKS (1)
2007/0288,686 Optimized placement policy for solid state storage devices 82 2006
 
BROADCOM CORPORATION (1)
6,658,016 Packet switching fabric having a segmented ring with token based resource control protocol and output queuing control 85 2000
 
BROOKE, LAWRENCE L. (1)
7,126,399 Memory interface phase-shift circuitry to support multiple frequency ranges 65 2004
 
CASCADE SEMICONDUCTOR CORPORATION (1)
2004/0047,228 Asynchronous hidden refresh of semiconductor memory 63 2003
 
CHEERTEK INC. (1)
2006/0112,214 Method for applying downgraded DRAM to an electronic device and the electronic device thereof 60 2005
 
CISCO TECHNOLOGY, INC. (1)
7,606,245 Distributed packet processing architecture for network access servers 60 2005
 
COMPUTERVISION CORPORATION (1)
4,888,687 Memory control system 57 1987
 
CSELT - CENTRO STUDI E LABORATORI TELECOMUNICAZIONI S.P.A. (1)
4,345,319 Self-correcting, solid-state-mass-memory organized by bits and with reconfiguration capability for a stored program control system 66 1979
 
DENSE-PAC MICROSYSTEMS, INC. (1)
2002/0089,831 Module with one side stacked memory 67 2001
 
DUX INC. (1)
5,966,727 Combination flash memory and dram memory board interleave-bypass memory access method, and memory access device incorporating both the same 118 1997
 
ELM TECHNOLOGY CORPORATION (1)
5,915,167 Three dimensional structure memory 520 1997
 
ELPIDA MEMORY, INC. (1)
5,332,922 Multi-chip semiconductor package 119 1991
 
ERICSSON AB (1)
7,007,095 Method and apparatus for unscheduled flow control in packet form 60 2001
 
FARADAY TECHNOLOGY CORP. (1)
2002/0004,897 Data processing apparatus for executing multiple instruction sets 77 2000
 
FormFactor, Inc. (1)
6,429,029 Concurrent design and subsequent partitioning of product and test die 155 1998
 
GENETICWARE CO., LTD. (1)
2003/0041,295 Method of defects recovery and status display of dram 66 2001
 
GLOBALFOUNDRIES INC. (1)
6,295,572 Integrated SCSI and ethernet controller on a PCI local bus 62 1994
 
HITACHI MAXELL, LTD. (1)
5,550,781 Semiconductor apparatus with two activating modes of different number of selected word lines at refreshing 60 1995
 
HITACHI TOHBU SEMICONDUCTOR, LTD. (1)
4,982,265 Semiconductor integrated circuit device and method of manufacturing the same 290 1988
 
HOECHST MARION ROUSSEL, INC. (1)
5,962,435 Method of lowering serum cholesterol levels with 2,6-di-alkyl-4-silyl-phenols 48 1997
 
HONDA GIKEN KOGYO KABUSHIKI KAISHA (1)
2001/0052,756 Electric power steering apparatus 2 2001
 
HONEYWELL INTERNATIONAL INC. (1)
6,765,812 Enhanced memory module architecture 75 2002
 
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE (1)
5,924,111 Method and system for interleaving data in multiple memory bank partitions 97 1995
 
INTEGRATED DEVICE TECHNOLOGY, INC. (1)
7,079,446 DRAM interface circuits having enhanced skew, slew rate and impedance control 65 2004
 
INTELLECTUAL VENTURES I LLC (1)
5,787,457 Cached synchronous DRAM architecture allowing concurrent DRAM operations 184 1996
 
INTERMEDICS, INC. (1)
5,963,429 Printed circuit substrate with cavities for encapsulating integrated circuits 96 1997
 
INTERNATIONAL MICROSYSTEMS, INC. (1)
6,473,831 Method and system for providing universal memory bus and module 74 1999
 
KONINKLIJKE PHILIPS ELECTRONICS N.V. (1)
2003/0046,431 Direct RTP delivery method and system over MPEG network 21 2002
 
KYOEI SANGYO CO., LTD. (1)
6,512,392 Method for testing semiconductor devices 67 2000
 
LG SEMICON CO., LTD. (1)
5,905,688 Auto power down circuit for a semiconductor memory device 63 1998
 
MICROSEMI SEMICONDUCTOR (U.S.) INC. (1)
6,047,073 Digital wavetable audio synthesizer with delay-based effects processing 94 1994
 
NEC ELECTRONICS CORPORATION (1)
4,841,440 Control processor for controlling a peripheral unit 166 1984
 
NETWORK APPLIANCE, INC. (1)
7,218,566 Power management of memory via wake/sleep cycles 66 2005
 
NORTH CAROLINA STATE UNIVERSITY (1)
2006/0181,953 SYSTEMS, METHODS AND DEVICES FOR PROVIDING VARIABLE-LATENCY WRITE OPERATIONS IN MEMORY DEVICES 63 2005
 
NXP B.V. (1)
5,193,072 Hidden refresh of a dynamic random access memory 81 1990
 
OCZ TECHNOLOGY (1)
2005/0278,474 Method of increasing DDR memory bandwidth in DDR SDRAM modules 61 2005
 
OKI ELECTRIC INDUSTRY CO., LTD. (1)
2005/0283,572 Semiconductor integrated circuit and power-saving control method thereof 54 2005
 
PANASONIC CORPORATION (1)
2005/0194,676 Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same 67 2005
 
POSTECH (1)
7,274,583 Memory system having multi-terminated multi-drop bus 60 2005
 
PROMOS TECHNOLOGIES INC. (1)
7,061,823 Limited output address register technique providing selectively variable write latency in DDR2 (double data rate two) integrated circuit memory devices 63 2004
 
QUALCOMM INCORPORATED (1)
7,075,175 Systems and methods for testing packaged dies 82 2004
 
ROCKSTAR CONSORTIUM US LP (1)
6,445,591 Multilayer circuit board 74 2000
 
SANDISK 3D LLC (1)
6,711,043 Three-dimensional memory cache system 70 2002
 
SANDISK IL LTD. (1)
2005/0027,928 SDRAM memory device with an embedded NAND flash controller 89 2003
 
SANDISK TECHNOLOGIES INC. (1)
7,173,863 Flash controller cache architecture 84 2004
 
SHARP KABUSHIKI KAISHA (1)
6,233,192 Semiconductor memory device 62 1999
 
SILICON INTEGRATED SYSTEMS CORP. (1)
2003/0158,995 Method for DRAM control with adjustable page size 75 2002
 
SMART MODULAR TECHNOLOGIES (AZ), INC. (1)
2008/0002,447 Memory supermodule utilizing point to point serial data links 57 2006
 
SONY CORPORATION (1)
7,233,541 Storage device 57 2005
 
SRC COMPUTERS, INC. (1)
2004/0236,877 Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM) 154 2004
 
ST. CLAIR INTELLECTUAL PROPERTY CONSULTANTS, INC. (1)
6,079,025 System and method of computer operating mode control for power consumption reduction 128 1998
 
Storage Technology Corporation (1)
5,448,511 Memory stack with an integrated interconnect and mounting structure 227 1994
 
SUPER TALENT TECHNOLOGY, CORP. (1)
7,243,185 Flash memory system with a high-speed flash controller 66 2004
 
SYNOLOGY INCORPORATED (1)
6,952,794 Method, system and apparatus for scanning newly added disk drives and automatically updating RAID configuration and rebuilding RAID data 103 2002
 
SYNOPSYS, INC. (1)
6,053,948 Method and apparatus using a memory model 72 1997
 
TANISYS TECHNOLOGY, INC. (1)
5,995,424 Synchronous memory test system 102 1997
 
THOMSON LICENSING (1)
2007/0091,696 Memory controller 56 2004
 
TOSHIBA STORAGE DEVICE CORPORATION (1)
6,324,120 Memory device having a variable data output length 64 2001
 
TRAN, DAVID N. (1)
2006/0117,160 Method to consolidate memory usage to reduce power consumption 68 2004
 
TWITTER, INC. (1)
6,381,668 Address mapping for system memory 91 1998
 
ULTRATERA CORPORATION (1)
6,713,856 Stacked chip package with enhanced thermal conductivity 68 2002
 
UNIRAM TECHNOLOGY, INC. (1)
6,216,246 Methods to make DRAM fully compatible with SRAM using error correction code (ECC) mechanism 117 1997
 
UNITED MEMORIES, INC. (1)
6,392,304 Multi-chip memory apparatus and associated method 83 1998
 
UNITED MICROELECTRONICS CORP. (1)
5,752,045 Power conservation in synchronous SRAM cache memory blocks of a computer system 91 1995
 
UNIVERSITY OF MARYLAND, BALTIMORE (1)
2006/0248,261 System and method for performing multi-rank command scheduling in DDR SDRAM memory systems 50 2006
 
UT AUTOMOTIVE DEARBORN, INC. (1)
4,698,748 Power-conserving control system for turning-off the power and the clocking for data transactions upon certain system inactivity 372 1983
 
VACHELLIA, LLC (1)
6,338,113 Memory module system having multiple memory modules 129 1998
 
VERSYSS INCORPORATED, A DE CORP. (1)
4,796,232 Dual port memory controller 169 1987
 
Viking Components (1)
6,222,739 High-density computer module with stacked parallel-plane packaging 143 1999
 
WELLS FARGO FOOTHILL, INC. (1)
2006/0117,152 Transparent four rank memory module for standard two rank sub-systems 86 2004
 
XILINX, INC. (1)
6,917,219 Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice 127 2003
 
Other [Check patent profile for assignment information] (5)
5,252,807 Heated plate rapid thermal processor 214 1991
6,091,251 Discrete die burn-in for nonpackaged die 107 1997
6,757,751 High-speed, multiple-bank, stacked, and PCB-mounted memory module 78 2000
2002/0064,073 DRAM MODULE AND METHOD OF USING SRAM TO REPLACE DAMAGED DRAM CELL 63 2000
2002/0034,068 Stacked printed circuit board memory module and method of augmenting memory therein 67 2001

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
RAMBUS INC. (1)
8,537,601 Memory controller with selective data transmission delay 0 2012

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
3.5 Year Payment $1600.00 $800.00 $400.00 Jun 13, 2015
7.5 Year Payment $3600.00 $1800.00 $900.00 Jun 13, 2019
11.5 Year Payment $7400.00 $3700.00 $1850.00 Jun 13, 2023
Fee Large entity fee small entity fee micro entity fee
Surcharge - 3.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge - 7.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00