Scaleable array of micro-engines for waveform processing
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United States of America Patent
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Dec 13, 2011
Grant Date -
Jun 18, 2009
app pub date -
Dec 12, 2007
filing date -
Dec 12, 2007
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Abstract
A system for implementing waveform processing in a software defined radio (SDR) includes a scaleable array processor having a plurality of micro-engines (MEs) interconnected by a two dimensional topology. Each micro-engine includes multiple FIFOs for interconnecting to each other in the two dimensional topology. One micro-engine communicates with another adjacent micro-engine by way of the respective FIFOs. The micro-engines are dedicated to predetermined algorithms. The two dimensional topology includes an array of N×M micro-engines interconnected by the multiple FIFOs. The N×M are integer numbers of rows and columns, respectively, in the array of micro-engines. The micro-engines are dedicated to baseband processing of data for RF transmission or RF reception.
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