Low on resistance CMOS “wave” transistor for integrated circuit applications
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United States of America Patent
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Dec 20, 2011
Grant Date -
Oct 8, 2009
app pub date -
Apr 8, 2009
filing date -
Apr 8, 2008
priority date (Note) -
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Abstract
In one embodiment of the present invention an array of power transistors on a semiconductor chip has repeating patterns of two “wave” gates which have alternating longer and shorter horizontal sections which are offset mirror images of each other together with a third straight horizontal section. Alternating source and drain regions lie between adjacent gates. Contacts are located adjacent each side of sections of the “wave” gates which connect the ends of the horizontal sections of the “wave” gates.
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