Importance

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Abstract

In an information-processing apparatus including a plurality of modules and a first arbiter which arbitrates bus-access requests of the plurality of modules, at least one of the plurality of modules includes a plurality of submodules and a second arbiter which arbitrates bus-access requests of the plurality of submodules and transmits at least one of the bus-access requests of the plurality of submodules to the first arbiter. The first arbiter gives priority to the module which transmits many bus-access requests, or the module which made a previous bus access, and limits the number of consecutive accesses made by the same module, so as to control the priority of accessing the bus by the plurality of modules. The second arbiter controls priority of accessing the bus by the plurality of submodules according to the free state of a buffer of each submodule, or the access type, whereby the bus-access requests made by the plurality of modules can be arbitrated, thus increasing bus-use efficiency.

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First Claim