FPGA programming structure for ATPG test coverage
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United States of America Patent
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Jan 3, 2012
Grant Date -
Jun 5, 2008
app pub date -
Nov 30, 2006
filing date -
Nov 30, 2006
priority date (Note) -
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Abstract
Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic. Some embodiments of the present invention provide for a method for testing functional logic block of an application-specific standard product (ASSP) in a programmable logic device, the method comprising: storing an input value into a register; passing the input value from the register to combinatorial logic; producing an output value from the combinatorial logic; passing the output value from the combinatorial logic to the register; saving the output value in the register; and reading the output value out of the register.
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