Methods and apparatus for integrated circuit having on chip capacitor with eddy current reductions
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United States of America Patent
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Jan 10, 2012
Grant Date -
Jan 28, 2010
app pub date -
Jul 24, 2008
filing date -
Jul 24, 2008
priority date (Note) -
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Abstract
Methods and apparatus for providing an integrated circuit including a substrate having a magnetic field sensor, first and second conductive layers generally parallel to the substrate, and a dielectric layer disposed between the first and second conductive layers such that the first and second conductive layers and the dielectric layer form a capacitor, wherein a slot is formed in at least one of the first and second conductive layers proximate the magnetic field sensor for reducing eddy currents in the first and second conductive layers.
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