Instruction fetch pipeline for superscalar digital signal processors and method of operation thereof
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United States of America Patent
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Jan 10, 2012
Grant Date -
Mar 4, 2010
app pub date -
Sep 4, 2008
filing date -
Sep 4, 2008
priority date (Note) -
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Abstract
A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop instruction, and b) provide a tight loop instruction target address. The next PC value generator further includes a next PC value logic having a plurality of inputs: a first input coupled to an output of the discontinuity decoder, and a second input coupled to an output of the tight loop decoder. The next PC value logic provides as an output, without a stall, a control signal that a next PC value is to be loaded with the tight loop instruction target address if: the discontinuity decoder detects a discontinuity instruction, and the tight loop decoder detects a tight loop instruction.
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