Method and apparatus for testing semiconductor devices with autonomous expected value generation
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United States of America Patent
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Jan 10, 2012
Grant Date -
Feb 25, 2010
app pub date -
Aug 19, 2008
filing date -
Aug 19, 2008
priority date (Note) -
Expired
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Abstract
Method and apparatus for testing semiconductor devices with autonomous expected value generation is described. Examples of the invention can relate to apparatus for interfacing a tester and a semiconductor device under test (DUT). An apparatus can include output processing logic configured to receive test result signals from the DUT responsive to testing by the tester, the output processing logic voting a logic value of a majority of the test result signals as a correct logic value; and memory configured to store indications of whether each of the test result signals has the correct logic value.
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