US Patent No: 8,099,618 - Analytics, PDF, Full Text and PAIR Access

Number of patents in Portfolio can not be more than 2000

Methods and devices for treating and processing data

ALSO PUBLISHED AS: 20090100286

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Abstract

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A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
PACT XPP TECHNOLOGIES AGZURICH84

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Baumgarte, Volker Munchen, DE 36 211
Vorbach, Martin Karlsruhe, DE 211 2807

Cited Art Landscape

Patent Info (Count) # Cites Year
 
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UNIVERSITY OF WASHINGTON (3)
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INFINEON TECHNOLOGIES AG (2)
6,717,436 Reconfigurable gate array 106 2002
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5,541,530 Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks 152 1995
5,815,726 Coarse-grained look-up table architecture 220 1995
6,020,758 Partially reconfigurable programmable logic device 116 1996
5,859,544 Dynamic configurable elements for programmable logic devices 117 1996
5,828,229 Programmable logic array integrated circuits 157 1997
6,085,317 Reconfigurable computer architecture using programmable logic devices 168 1997
6,134,166 Programmable logic array integrated circuit incorporating a first-in first-out memory 54 1998
6,247,147 Enhanced embedded logic analyzer 106 1998
6,216,223 Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor 73 1999
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6,658,564 Reconfigurable programmable logic device computer system 97 1999
2001/0032,305 Methods and apparatus for dual-use coprocessing/debug interface 119 2001
7,340,596 Embedded processor with watchdog timer for programmable logic 55 2001
2002/0124,238 Software-to-hardware compiler 60 2001
6,538,470 Devices and methods with programmable logic and digital signal processing regions 207 2001
6,525,678 Configuring a programmable logic device 74 2001
7,000,161 Reconfigurable programmable logic system with configuration recovery mode 64 2002
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* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
CYPRESS SEMICONDUCTOR CORPORATION (3)
8,441,298 Analog bus sharing using transmission gates 2 2009
* 2011/0026,519 DYNAMICALLY RECONFIGURABLE ANALOG ROUTING CIRCUITS AND METHODS FOR SYSTEM ON A CHIP 2 2010
8,890,600 Bus sharing scheme 0 2013
 
INTEL CORPORATION (1)
* 2012/0169,746 METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING NON FRAME AWARE FREQUENCY SELECTION 0 2011
* Cited By Examiner

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