US Patent No: 8,099,618 - Analytics, PDF, Full Text and PAIR Access

Number of patents in Portfolio can not be more than 2000

Methods and devices for treating and processing data

ALSO PUBLISHED AS: 20090100286

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
PACT XPP TECHNOLOGIES AGZURICH86

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Baumgarte, Volker Munchen, DE 37 217
Vorbach, Martin Karlsruhe, DE 213 2856

Cited Art Landscape

Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (7)
5,535,406 Virtual processor module including a reconfigurable programmable matrix 155 1993
5,675,757 Direct match data flow memory for data driven computing 56 1995
5,734,869 High speed logic circuit simulator 53 1995
6,285,624 Multilevel memory access method 52 2000
6,398,383 Flashlight carriable on one's person 59 2000
2001/0001,860 Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith 49 2001
2003/0086,300 FPGA coprocessing system 101 2002
 
TRANSWITCH CORPORATION (1)
6,754,805 Method and apparatus for configurable multi-cell digital signal processing employing global parallel configuration 65 2000
 
Bull HN Information Systems Inc. (1)
5,435,000 Central processing unit using dual basic processing units and combined result bus 35 1993
 
SERENITY SYSTEMS, LLC (1)
5,675,777 Architecture for minimal instruction set computing system 51 1995
 
TECH SEARCH LLC (1)
5,574,927 RISC architecture computer configured for emulation of the instruction set of a target computer 242 1994
 
XILINX, INC. (81)
4,706,216 Configurable logic element 500 1985
4,870,302 Configurable electrical circuit having configurable logic elements and configurable interconnects 735 1988
5,343,406 Distributed memory architecture for a configurable logic array and method for using distributed memory 263 1989
RE34363 Configurable electrical circuit having configurable logic elements and configurable interconnects 598 1991
RE34444 Programmable logic device 99 1991
5,243,238 Configurable cellular array 160 1991
5,365,125 Logic cell for field programmable gate array having optional internal feedback and optional cascade 254 1992
5,386,154 Compact logic cell for field programmable gate array chip 66 1992
5,469,003 Hierarchically connectable configurable cellular array 339 1993
5,455,525 Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array 380 1993
5,430,687 Programmable logic device including a parallel input device for loading memory cells 211 1994
5,781,756 Programmable logic device with partially configurable memory cells and a method for configuration 77 1994
5,426,378 Programmable logic device which stores more than one configuration and means for switching configurations 442 1994
5,450,022 Structure and method for configuration of a field programmable gate array 63 1994
5,521,837 Timing driven method for laying out a user's circuit onto a programmable integrated circuit device 182 1995
5,491,353 Configurable cellular array 111 1995
5,504,439 I/O interface cell for use with optional pad 88 1995
5,600,597 Register protection structure for FPGA 77 1995
5,701,091 Routing resources for hierarchical FPGA 70 1995
5,748,979 Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table 134 1995
5,752,035 Method for compiling and executing programs for reprogrammable instruction set accelerator 180 1995
5,583,450 Sequencer for a time multiplexed programmable logic device 155 1995
5,646,545 Time multiplexed programmable logic device 340 1995
5,778,439 Programmable logic device with hierarchical confiquration and state storage 165 1995
5,705,938 Programmable switch for FPGA input/output signals 185 1995
5,642,058 Periphery input/output interconnect structure 62 1995
5,815,004 Multi-buffered configurable logic block output lines in a field programmable gate array 140 1995
5,608,342 Hierarchical programming of electrically configurable integrated circuits 55 1995
5,656,950 Interconnect lines including tri-directional buffer circuits 83 1995
5,675,262 Fast carry-out scheme in a field programmable gate array 65 1995
5,898,602 Carry chain circuit with flexible carry function for implementing arithmetic and logical functions 127 1996
5,635,851 Read and writable data bus particularly for programmable logic devices 71 1996
5,754,459 Multiplier circuit design for a programmable logic device 157 1996
6,023,564 Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions 75 1996
5,831,448 Function unit for fine-gained FPGA 115 1996
5,933,023 FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines 205 1996
5,821,774 Structure and method for arithmetic function implementation in an EPLD having high speed product term allocation structure 60 1996
5,801,547 Embedded memory for field programmable gate array 141 1996
5,844,422 State saving and restoration in reprogrammable FPGAs 137 1996
6,427,156 Configurable logic block with AND gate for efficient multiplication in FPGAS 81 1997
6,047,115 Method for configuring FPGA memory planes for virtual hardware computation 129 1997
6,011,407 Field programmable gate array with dedicated computer bus interface and method for configuring both 173 1997
6,078,736 Method of designing FPGAs for dynamically reconfigurable computing 168 1997
5,892,961 Field programmable gate array having programming instructions in the configuration bitstream 224 1997
5,936,424 High speed bus with tree structure for selecting bus driver 104 1997
6,026,481 Microprocessor with distributed registers accessible by programmable logic device 102 1997
6,212,650 Interactive dubug tool for programmable circuits 95 1997
6,049,222 Configuring an FPGA using embedded memory 150 1997
6,230,307 System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects 222 1998
6,154,049 Multiplier fabric for use in field programmable gate arrays 138 1998
6,084,429 PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays 258 1998
5,978,260 Method of time multiplexing a programmable logic device 139 1998
6,137,307 Structure and method for loading wide frames of data from a narrow input bus 62 1998
6,172,520 FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA 103 1999
6,198,304 Programmable logic device 83 1999
6,105,105 Data processing system using configuration select logic, an instruction store, and sequencing logic during instruction execution 95 1999
6,263,430 Method of time multiplexing a programmable logic device 81 1999
6,204,687 Method and structure for configuring FPGAS 186 1999
6,434,642 FIFO memory system and method with improved determination of full and empty conditions and amount of data stored 79 1999
RE37195 Programmable switch for FPGA input/output signals 125 2000
6,496,971 Supporting multiple FPGA configuration modes using dedicated on-chip processor 141 2000
6,487,709 Run-time routing for programmable logic devices 210 2000
6,154,048 Structure and method for loading narrow frames of data from a wide input bus 63 2000
6,150,839 Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM 97 2000
6,421,817 System and method of computation in a programmable logic device using virtual instructions 110 2000
6,201,406 FPGA configurable by two types of bitstreams 63 2000
6,362,650 Method and apparatus for incorporating a multiplier into an FPGA 141 2000
6,373,779 Block RAM having multiple configurable write modes for use in a field programmable gate array 71 2000
6,518,787 Input/output architecture for efficient configuration of programmable input/output cells 103 2000
6,836,842 Method of partial reconfiguration of a PLD in which only updated portions of configuration data are selected for reconfiguring the PLD 44 2001
6,802,026 Parameterizable and reconfigurable debugger core generators 79 2001
6,480,954 Method of time multiplexing a programmable logic device 241 2001
6,886,092 Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion 74 2001
6,668,237 Run-time reconfigurable testing of programmable logic devices 101 2002
6,476,634 ALU implementation in single PLD logic cell 82 2002
7,038,952 Block RAM with embedded FIFO buffer 60 2004
2005/0144,210 Programmable logic device with dynamic DSP architecture 89 2004
2005/0144,215 Applications of cascading DSP slices 117 2004
2006/0230,094 Digital signal processing circuit having input register blocks 86 2006
2006/0230,096 Digital signal processing circuit having an adder circuit with carry-outs 84 2006
7,759,968 Method of and system for verifying configuration data 43 2006
 
UNIVERSITY OF HAWAII (1)
5,574,930 Computer system and method using functional memory 136 1994
 
HUGHES ELECTRONICS CORPORATION (3)
4,498,134 Segregator functional plane for use in a modular array processor 112 1982
6,145,072 Independently non-homogeneously dynamically reconfigurable two dimensional interprocessor communication topology for SIMD multi-processors and apparatus for implementing same 139 1994
5,901,279 Connection of spares between multiple programmable devices 68 1996
 
Wavetracer, Inc. (1)
5,193,202 Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor 96 1990
 
LOCKHEED MARTIN CORPORATION (1)
4,901,268 Multiple function data processor 97 1988
 
BROADCOM CORPORATION (8)
5,915,123 Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements 157 1997
6,108,760 Method and apparatus for position independent reconfiguration in a network of multiple context processing elements 93 1997
6,122,719 Method and apparatus for retiming in a network of multiple context processing elements 92 1997
6,457,116 Method and apparatus for controlling contexts of multiple context processing elements in a network of multiple context processing elements 153 1999
6,745,317 Three level direct communication connections between neighboring multiple context processing elements 46 1999
6,624,819 Method and system for providing a flexible and efficient processor for use in a graphics processing system 46 2000
6,553,479 Local control of multiple context processing elements with major contexts and minor contexts 114 2002
6,751,722 Local control of multiple context processing elements with configuration contexts 101 2003
 
PACT GMBH (1)
7,237,087 Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells 58 2002
 
PACT INFORMATIONSTECHNOLOGIE GMBH (2)
6,480,937 Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)-- 105 2001
6,687,788 Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.) 76 2002
 
HEWLETT-PACKARD COMPANY (1)
4,852,043 Daisy-chain bus system with truncation circuitry for failsoft bypass of defective sub-bus subsystem 81 1987
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (21)
4,663,706 Multiprocessor multisystem communications network 172 1983
5,226,122 Programmable logic system for filtering commands to a microprocessor 116 1987
5,014,193 Dynamically configurable portable computer system 208 1988
5,203,005 Cell structure for linear array wafer scale integration architecture with capability to open boundary I/O bus without neighbor acknowledgement 74 1989
5,036,493 System and method for reducing power usage by multiple memory modules 94 1990
5,287,472 Memory system using linear array wafer scale integration architecture 104 1990
5,353,432 Interactive method for configuration of computer system and circuit boards with user specification of system resources and computer resolution of resource conflicts 113 1991
5,568,624 Byte-compare operation for high-performance processor 79 1993
5,996,083 Microprocessor having software controllable power consumption 236 1995
6,003,143 Tool and method for diagnosing and correcting errors in a computer program 111 1997
5,857,097 Method for identifying reasons for dynamic stall cycles during the execution of a program 94 1997
5,884,075 Conflict resolution using self-contained virtual devices 78 1997
6,125,408 Resource type prioritization in generating a device configuration 82 1997
6,035,371 Method and apparatus for addressing a static random access memory device based on signals for addressing a dynamic memory access device 52 1997
6,157,214 Wiring of cells in logic arrays 53 1999
6,507,947 Programmatic synthesis of processor element arrays 177 1999
6,434,672 Methods and apparatus for improving system performance with a shared cache memory 46 2000
2002/0099,759 Load balancer with starvation avoidance 46 2001
2002/0186,837 Multiple prime number generation using a parallel prime number search algorithm 1 2001
6,782,445 Memory and instructions in computer architecture containing processor and coprocessor 65 2001
6,725,334 Method and system for exclusive two-level caching in a chip-multiprocessor 69 2001
 
U.S. PHILIPS CORPORATION (2)
5,055,997 System with plurality of processing elememts each generates respective instruction based upon portions of individual word received from a crossbar switch 122 1990
5,659,797 Sparc RISC based computer system including a single chip processor with memory management and DMA units coupled to a DRAM interface 116 1992
 
PACT XPP TECHNOLOGIES AG (24)
5,943,242 Dynamically reconfigurable data processing system 103 1995
6,021,490 Run-time reconfiguration method for programmable units 96 1997
6,038,650 Method for the automatic address generation of modules within clusters comprised of a plurality of these modules 68 1997
6,081,903 Method of the self-synchronization of configurable elements of a programmable unit 95 1997
6,088,795 Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like) 81 1997
6,119,181 I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures 99 1997
6,425,068 UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAYS (EPGAS) 92 1997
6,405,299 Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity 95 1998
6,859,869 Data processing system 44 1999
6,728,871 Runtime configurable arithmetic and logic cell 60 1999
6,338,106 I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures 98 1999
6,542,998 Method of self-synchronization of configurable elements of a programmable module 88 1999
6,526,520 Method of self-synchronization of configurable elements of a programmable unit 66 2000
6,697,979 Method of repairing integrated circuits 110 2000
6,477,643 Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like) 155 2000
6,571,381 Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.) 90 2001
6,513,077 I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures 67 2001
7,595,659 Logic cell array and bus system 43 2001
7,010,667 Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity 166 2002
7,657,877 Method for processing data 46 2002
7,028,107 Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like) 51 2002
6,721,830 I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures 64 2002
2007/0083,730 Data processing device and method 75 2004
7,650,448 I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures 41 2008
 
DAIMLERCHRYSLER AG (1)
6,435,054 Shifting device for a manual gear transmission 19 2000
 
STAR SEMICONDUCTOR (1)
5,287,511 Architectures and methods for dividing processing tasks into tasks for a programmable real time signal processor and tasks for a decision making microprocessor interfacing therewith 80 1991
 
OKI ELECTRIC INDUSTRY CO., LTD. (1)
4,686,386 Power-down circuits for dynamic MOS integrated circuits 114 1985
 
NEORAM LLC (1)
5,838,165 High performance self modifying on-the-fly alterable logic FPGA, architecture and method 326 1996
 
Sun Microsystems, Inc. (8)
5,119,290 Alias address support 65 1990
5,996,048 Inclusion vector architecture for a level two cache 53 1997
5,838,988 Computer product for precise architectural update in an out-of-order processor 59 1997
6,240,502 Apparatus for dynamically reconfiguring a processor 72 1997
6,490,695 Platform independent memory image analysis architecture for debugging a computer program 70 1999
6,286,134 Instruction selection in a multi-platform environment 94 1999
6,704,816 Method and apparatus for executing standard functions in a computer system using a field programmable gate array 153 2000
7,036,114 Method and apparatus for cycle-based computation 40 2002
 
Hughes Aircraft Company (2)
5,021,947 Data-flow multiprocessor architecture with three dimensional multistage interconnection network for efficient signal and data processing 269 1990
5,379,444 Array of one-bit processors each having only one bit of memory 74 1994
 
ITT CORPORATION (1)
4,852,048 Single instruction multiple data (SIMD) cellular array processing apparatus employing a common bus where a first number of bits manifest a first bus portion and a second number of bits manifest a second bus portion 115 1985
 
FUJI XEROX CO., LTD. (2)
5,204,935 Programmable fuzzy logic circuits 93 1992
5,448,186 Field-programmable gate array 152 1994
 
INTELLECTUAL VENTURES II LLC (1)
5,687,325 Application specific field programmable gate array 255 1996
 
ARM LIMITED (1)
5,525,971 Integrated circuit 82 1994
 
LOCKHEED MARTIN ROLM MIL-SPEC CORP. (1)
5,418,953 Method for automated deployment of a software program onto a multi-processor architecture 91 1993
 
Versity Design, Inc. (1)
6,321,366 Timing-insensitive glitch-free logic system and method 129 1998
 
INTERSIL CORPORATION (1)
4,498,172 System for polynomial division self-testing of digital networks 110 1982
 
TEXAS INSTRUMENTS INCORPORATED (6)
5,212,777 Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation 348 1989
5,522,083 Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors 211 1994
5,532,957 Field reconfigurable logic/memory array 108 1995
6,279,077 Bus interface buffer control in a microprocessor 105 1997
5,960,193 Apparatus and system for sum of plural absolute differences 111 1997
6,256,724 Digital signal processor with efficiently connectable hardware co-processor 63 1999
 
COMPUTER UPGRADE CORPORATION (1)
5,034,914 Optical disk data storage method and apparatus with buffered interface 150 1988
 
SILICON STORAGE TECHNOLOGY, INC. (1)
6,173,419 Field programmable gate array (FPGA) emulator for debugging software 107 1998
 
MINISTRY OF ECONOMY, TRADE AND INDUSTRY (1)
6,681,388 Method and compiler for rearranging array data into sub-arrays of consecutively-addressed elements for distribution processing 58 1999
 
INTELLECTUAL VENTURES HOLDING 6 LLC (1)
6,173,434 Dynamically-configurable digital processor using method for relocating logic array modules 83 1997
 
MICRON TECHNOLOGY, INC. (2)
6,105,106 Computer system, memory device and shift register including a balanced switching circuit with series connected transfer gates which are selectively clocked for fast switching times 59 1997
6,516,382 Memory device balanced switching circuit and method of controlling an array of transfer gates for fast switching times 53 2001
 
XEROX CORPORATION (1)
5,924,119 Consistent packet switched memory bus for shared memory multiprocessors 81 1994
 
UNIVERSITY OF SOUTHWESTERN LOUISIANA, A UNIVERSITY OF LA (1)
4,571,736 Digital communication system employing differential coding and sample robbing 59 1983
 
CAL. MEDIA, L.L.C. (1)
5,675,743 Multi-media server 95 1995
 
SEASOUND, LLC (2)
5,361,373 Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor 274 1992
5,600,845 Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor 193 1994
 
VERISITY DESIGN, INC. (1)
2002/0152,060 Inter-chip communication system 86 2001
 
COX COMMUNICATIONS, INC. (1)
5,867,723 Advanced massively parallel computer with a secondary storage device coupled through a secondary storage interface 99 1996
 
PARALLEL SIMULATION TECHNOLOGY, LLC (1)
5,418,952 Parallel processor cell computer system 141 1992
 
UNIVERSITY OF KENTUCKY RESEARCH FOUNDATION (2)
6,202,182 Method and apparatus for testing field programmable gate arrays 105 1998
6,631,487 On-line testing of field programmable gate array resources 68 2000
 
Mitsubishi Electric Semiconductor Software Co., Ltd. (2)
5,657,330 Single-chip microprocessor with built-in self-testing function 85 1995
6,185,731 Real time debugger for a microcomputer 61 1995
 
GOOGLE INC. (3)
6,076,157 Method and apparatus to force a thread switch in a multithreaded processor 173 1997
6,212,544 Altering thread priorities in a multithreaded processor 247 1997
6,757,847 Synchronization for system analysis 64 1999
 
LG ELECTRONICS INC. (1)
4,939,641 Multi-processor system with cache memories 81 1988
 
KONINKLIJKE PHILIPS ELECTRONICS N.V. (1)
2002/0083,308 Data processing device with a configurable functional unit 57 2001
 
SHARP KABUSHIKI KAISHA (3)
5,115,510 Multistage data flow processor with instruction packet, fetch, storage transmission and address generation controlled by destination information 95 1988
5,327,125 Apparatus for and method of converting a sampling frequency according to a data driven type processing 115 1993
5,870,620 Data driven type information processor with reduced instruction execution requirements 55 1996
 
Hudson Soft Co., Ltd. (1)
5,530,873 Method and apparatus for processing interruption 79 1993
 
SILICON GRAPHICS INTERNATIONAL CORP. (1)
5,841,973 Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue's tail pointer structure in local memory 137 1996
 
LATROSSE TECHNOLOGIES, L.L.C. (1)
5,887,165 Dynamically reconfigurable hardware system for real-time control of processes 121 1997
 
SP TECHNOLOGY CORP., 1150 QUAIL LAKE LOOP, COLORADO SPRINGS, CO 80906 A CORP. OF DE (1)
5,303,172 Pipelined combination and vector signal processor 100 1988
 
SILICON GRAPHICS, INC. (1)
6,496,902 Vector and scalar data cache for a vector multiprocessor 88 1998
 
CRYSTAL SEMICONDUCTOR CORPORATION (1)
6,055,619 Circuits, system, and methods for processing multiple data streams 138 1997
 
IPG ELECTRONICS 503 LIMITED (1)
5,103,311 Data processing module and video processing system incorporating same 124 1990
 
KUBOTA U.S.A. INC. (1)
4,959,781 System for assigning interrupts to least busy processor that already loaded same class of interrupt routines 68 1988
 
AGILENT TECHNOLOGIES, INC. (1)
4,720,778 Software debugging analyzer 83 1985
 
TAYLOR MADE GOLF COMPANY, INC. (1)
5,294,119 Vibration-damping device for a golf club 115 1992
 
CYPRESS SEMICONDUCTOR CORPORATION (1)
6,538,468 Method and apparatus for multiple boot-up functionalities for a programmable logic device (PLD) 109 2000
 
GEO SEMICONDUCTOR INC. (2)
4,739,474 Geometric-arithmetic parallel processor 176 1983
5,421,019 Parallel data processor 108 1992
 
EXAR CORPORATION (1)
6,633,181 Multi-scale programmable array 88 1999
 
THE UNIVERSITY OF NORTH CAROLINA AT CHAPEL HILL (1)
6,874,108 Fault tolerant operation of reconfigurable devices utilizing an adjustable system clock 65 2002
 
AKAMAI TECHNOLOGIES, INC. (5)
2009/0132,648 CONTENT DELIVERY AND GLOBAL TRAFFIC MANAGEMENT NETWORK SYSTEM 38 2009
2009/0132,648 CONTENT DELIVERY AND GLOBAL TRAFFIC MANAGEMENT NETWORK SYSTEM 38 2009
2009/0132,648 CONTENT DELIVERY AND GLOBAL TRAFFIC MANAGEMENT NETWORK SYSTEM 38 2009
2009/0132,648 CONTENT DELIVERY AND GLOBAL TRAFFIC MANAGEMENT NETWORK SYSTEM 38 2009
2009/0132,648 CONTENT DELIVERY AND GLOBAL TRAFFIC MANAGEMENT NETWORK SYSTEM 38 2009
 
MICROPUMP, INC. (1)
5,865,239 Method for making herringbone gears 53 1997
 
CANON KABUSHIKI KAISHA (2)
6,118,724 Memory controller architecture 71 1998
6,507,898 Reconfigurable data cache controller 75 1998
 
MICRAL, INC. (1)
5,412,795 State machine having a variable timing mechanism for varying the duration of logical output states of the state machine based on variation in the clock frequency 56 1992
 
LUCENT TECHNOLOGIES INC. (1)
6,086,628 Power-related hardware-software co-synthesis of heterogeneous distributed embedded systems 121 1998
 
CAMBRIDGE MANAGEMENT CORPORATION (1)
5,287,532 Processor elements having multi-byte structure shift register for shifting data either byte wise or bit wise with single-bit output formed at bit positions thereof spaced by one byte 70 1990
 
MOTOROLA, INC. (2)
5,493,239 Circuit and method of configuring a field programmable gate array 147 1995
5,649,179 Dynamic instruction allocation for a SIMD processor 76 1995
 
GENERAL SEMICONDUCTOR, INC. (1)
4,414,547 Storage logic array having two conductor data column 83 1981
 
INTEL CORPORATION (31)
4,910,665 Distributed processing system including reconfigurable elements 98 1986
5,023,775 Software programmable logic array utilizing "and" and "or" gates 120 1990
5,392,437 Method and apparatus for independently stopping and restarting functional units 217 1992
5,634,131 Method and apparatus for independently stopping and restarting functional units 134 1994
5,889,982 Method and apparatus for generating event handler vectors based on both operating mode and event type 81 1995
5,652,894 Method and apparatus for providing power saving modes to a pipelined processor 109 1995
5,696,976 Protocol for interrupt bus arbitration in a multi-processor system 66 1996
6,389,579 Reconfigurable logic for table lookup 100 1999
6,243,808 Digital data bit order conversion using universal switch matrix comprising rows of bit swapping selector groups 100 1999
6,298,472 Behavioral silicon construct architecture and mapping 133 1999
6,347,346 Local memory unit system with global access for use on reconfigurable chips 142 1999
6,370,596 Logic flag registers for monitoring processing system events 97 1999
6,341,318 DMA data streaming 109 1999
6,606,704 Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode 130 1999
6,288,566 Configuration state memory for functional blocks on a reconfigurable chip 102 1999
6,311,200 Reconfigurable program sum of products generator 98 1999
6,349,346 Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit 105 1999
6,519,674 Configuration bits layout 88 2000
6,539,477 System and method for control synthesis using a reachable states look-up table 100 2000
6,871,341 Adaptive scheduling of function cells in dynamic reconfigurable logic 73 2000
6,282,627 Integrated processor and programmable data path chip for reconfigurable computing 255 2000
6,708,325 Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic 77 2000
6,392,912 Loading data plane on reconfigurable chip 97 2001
2002/0143,505 Implementing a finite state machine using concurrent finite state machines with delayed communications and no shared control signals 69 2001
2002/0013,861 Method and apparatus for low overhead multithreaded communication in a parallel processing environment 78 2001
2003/0056,091 Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations 71 2001
2003/0055,861 Multipler unit in reconfigurable chip 91 2001
2003/0052,711 Despreader/correlator unit for use in reconfigurable chip 67 2001
2002/0038,414 Address generator for local system memory in reconfigurable logic chip 66 2001
6,868,476 Software controlled content addressable memory in a general purpose execution datapath 69 2002
7,216,204 Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment 59 2002
 
Mitsubishi Denki Kabushiki Kaisha (4)
5,047,924 Microcomputer 73 1988
5,010,401 Picture coding and decoding apparatus using vector quantization 137 1989
5,355,508 Parallel data processing system combining a SIMD unit with a MIMD unit and sharing a common bus, memory, and system controller 116 1992
5,237,686 Multiprocessor type time varying image encoding system and image processor with memory bus control table for arbitration priority 119 1992
 
MORGAN STANLEY & CO., INCORPORATED (1)
6,049,866 Method and system for an efficient user mode cache manipulation using a simulated instruction 69 1996
 
TAROFISS DATA LIMITED LIABILITY COMPANY (3)
6,178,494 Modular, hybrid processor and method for producing a modular, hybrid processor 69 1996
5,802,290 Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed 230 1996
6,289,440 Virtual computer of plural FPG's successively reconfigured in response to a succession of inputs 99 1999
 
UNITED TECHNOLOGIES CORPORATION (1)
4,623,997 Coherent interface with wraparound receive and transmit memories 60 1984
 
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. (1)
7,043,416 System and method for state restoration in a diagnostic module for a high-speed microprocessor 45 2001
 
Cadence Design Systems, Inc. (5)
5,680,583 Method and apparatus for a trace buffer in an emulation system 86 1994
5,606,698 Method for deriving optimal code schedule sequences from synchronous dataflow graphs 67 1995
6,020,760 I/O buffer circuit with pin multiplexing 106 1997
6,389,379 Converification system and method 156 1998
6,421,808 Hardware design language for the design of integrated circuits 82 1999
 
POLYTECHNIC UNIVERSITY (1)
6,449,283 Methods and apparatus for providing a fast ring reservation arbitration 84 1999
 
CHAMELEON SEMICONDUCTOR (2)
5,966,534 Method for compiling high level programming languages into an integrated processor with reconfigurable logic 191 1997
5,970,254 Integrated processor and programmable data path chip for reconfigurable computing 260 1997
 
Thomson-CSF (1)
4,891,810 Reconfigurable computing device 107 1987
 
Echelon Corporation (2)
5,113,498 Input/output section for an intelligent cell which provides sensing, bidirectional communications and control 142 1990
5,844,888 Network and intelligent cell for providing sensing, bidirectional communications and control 140 1995
 
INTERGRAPH HARDWARE TECHNOLOGIES COMPANY (1)
5,274,593 High speed redundant rows and columns for semiconductor memories 77 1990
 
GIGA OPERATIONS CORPORATION (1)
5,857,109 Programmable logic device for real time video processing 119 1995
 
QUICKTURN DESIGN SYSTEMS, INC. (1)
5,036,473 Method of using electronically reconfigurable logic circuits 285 1989
 
MASSACHUSETTS INSTITUTE OF TECHNOLOGY (9)
5,596,742 Virtual interconnections for reconfigurable logic systems 216 1993
5,440,538 Communication system with redundant links and data bit time multiplexing 84 1993
5,742,180 Dynamically programmable gate array with multiple contexts 287 1995
6,052,773 DPGA-coupled microprocessors 194 1995
5,761,484 Virtual interconnections for reconfigurable logic systems 185 1995
5,956,518 Intermediate-grain reconfigurable processing device 191 1996
6,127,908 Microelectro-mechanical system actuator device and reconfigurable circuits utilizing same 183 1997
5,927,423 Reconfigurable footprint mechanism for omnidirectional vehicles 96 1998
6,266,760 Intermediate-grain reconfigurable processing device 123 1999
 
NEC CORPORATION (2)
4,591,979 Data-flow-type digital processing apparatus 110 1983
2001/0003,834 Interprocessor communication method and multiprocessor 54 2000
 
QUICKFLEX, INC. (1)
6,539,438 Reconfigurable computing system and method and apparatus employing same 102 1999
 
NEC ELECTRONICS CORPORATION (1)
5,926,638 Program debugging system for debugging a program having graphical user interface 87 1997
 
QUICKLOGIC CORPORATION (4)
5,773,994 Method and apparatus for implementing an internal tri-state bus within a programmable logic circuit 79 1995
5,892,370 Clock network for field programmable gate array 68 1997
6,426,649 Architecture for field programmable gate array 122 2000
6,483,343 Configurable computational unit embedded in a programmable device 241 2000
 
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. (1)
6,434,699 Encryption processor with shared memory interconnect 121 2000
 
ZIILABS INC., LTD. (2)
6,977,649 3D graphics rendering with selective read suspend 50 1999
6,847,370 Planar byte memory organization with linear access 60 2002
 
Dell USA, L.P. (1)
5,530,946 Processor failure detection and recovery circuit in a dual processor computer system and method of operation thereof 117 1994
 
Walker-Estes Corporation (1)
5,301,284 Mixed-resolution, N-dimensional object space method and apparatus 110 1991
 
RPX CORPORATION (2)
5,611,049 System for accessing distributed data cache channel at each network node to pass requests and data 333 1994
5,804,986 Memory in a programmable logic device 100 1995
 
Matsushita Electric Industrial Co., Ltd. (8)
6,353,841 Reconfigurable processor devices 139 1998
6,523,107 Method and apparatus for providing instruction streams to a processing device 50 1998
6,252,792 Field programmable processor arrays 62 1999
6,262,908 Field programmable processor devices 56 1999
6,567,834 Implementation of multipliers in programmable arrays 56 2000
6,542,394 Field programmable processor arrays 51 2001
6,901,502 Integrated circuit with CPU and FPGA for reserved instructions execution with configuration diagnosis 59 2001
6,820,188 Method and apparatus for varying instruction streams provided to a processing device using masks 51 2003
 
ATMEL CORPORATION (4)
4,918,440 Programmable logic cell and array 168 1986
5,144,166 Programmable logic cell and array 354 1990
5,894,565 Field programmable gate array with distributed RAM and increased cell utilization 123 1996
6,014,509 Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells 134 1997
 
SONY CORPORATION (3)
5,477,525 Data destruction preventing method, recording apparatus provided with data destruction preventing capability, and disc recorded with guard band 56 1993
6,188,650 Recording and reproducing system having resume function 66 1998
7,010,687 Transmission apparatus, reception apparatus, transmission method, reception method and recording medium 48 2001
 
SAMSUNG ELECTRONICS CO., LTD. (7)
5,655,124 Selective power-down for high performance CPU/system 113 1995
5,732,209 Self-testing multi-processor die with internal compare points 141 1996
5,832,288 Element-select mechanism for a vector processor 39 1996
5,889,533 First-in-first-out device for graphic drawing engine 52 1997
6,381,624 Faster multiply/accumulator 51 1999
6,438,747 Programmatic iteration scheduling for parallel processors 95 1999
6,425,054 Multiprocessor operation in a multimedia signal processor 75 2000
 
WOLFGANG LERCHE (1)
6,657,457 Data transfer on reconfigurable chip 66 2000
 
LUJACK SYSTEMS LLC (1)
5,065,308 Processing cell for fault tolerant arrays 91 1991
 
COMTECH TELECOMMUNICATIONS CORP. (1)
5,532,693 Adaptive data compression system with systolic string matching logic 120 1994
 
RENESAS TECHNOLOGY CORP. (1)
6,928,523 Synchronous signal producing circuit for controlling a data ready signal indicative of end of access to a shared memory and thereby controlling synchronization between processor and coprocessor 55 2001
 
NXP B.V. (1)
5,537,580 Integrated circuit fabrication using state machine extraction from behavioral hardware description language 141 1994
 
RENESAS ELECTRONICS CORPORATION (5)
5,408,643 Watchdog timer with a non-masked interrupt masked only when a watchdog timer has been cleared 59 1992
5,915,099 Bus interface unit in a microprocessor for facilitating internal and external memory accesses 38 1997
6,598,128 Microprocessor having improved memory management unit and cache memory 52 1999
6,400,601 Nonvolatile semiconductor memory device 68 2000
2010/0306,602 SEMICONDUCTOR DEVICE AND ABNORMALITY DETECTING METHOD 33 2010
 
RENESAS ELECTRONICS AMERICA, INC. (1)
2008/0313,383 Processor for Virtual Machines and Method Therefor 37 2008
 
UNIVERSITY OF VIRGINIA ALUMNI PATENTS FOUNDATION, THE (1)
6,154,826 Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order 104 1997
 
IMEC VZW (1)
6,421,809 Method for determining a storage bandwidth optimized memory organization of an essentially digital device 128 1999
 
LATTICE SEMICONDUCTOR CORPORATION (11)
5,233,539 Programmable gate array with improved interconnect structure, input/output structure and configurable logic block 172 1989
5,015,884 Multiple array high performance programmable logic device family 136 1990
5,489,857 Flexible synchronous/asynchronous cell structure for a high density programmable logic device 102 1992
5,422,823 Programmable gate array device having cascaded means for function definition 150 1994
5,485,104 Logic allocator for a programmable logic device 95 1995
5,586,044 Array of configurable logic blocks including cascadable lookup tables 93 1995
5,559,450 Field programmable gate array with multi-port RAM 182 1995
5,587,921 Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer 91 1995
5,892,962 FPGA-based processor 268 1996
6,034,538 Virtual logic system for reconfigurable hardware 144 1998
6,803,787 State machine in a programmable logic device 67 2002
 
USA AS REPRESENTED BY THE ADMINISTRATOR OF THE NASA (1)
5,548,773 Digital parallel processor array for optimum path planning 109 1993
 
FIFTH GENERATION COMPUTER CORP. (1)
4,860,201 Binary tree parallel processor 231 1986
 
Sony Pictures Entertainment Inc. (1)
6,539,415 Method and apparatus for the allocation of audio/video tasks in a network system 52 1997
 
GLOBALFOUNDRIES INC. (2)
5,627,992 Organization of an integrated cache unit for flexible usage in supporting microprocessor operations 68 1995
6,096,091 Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip 171 1998
 
WASHINGTON UNIVERSITY (3)
5,208,491 Field programmable gate array 405 1992
6,023,742 Reconfigurable computing architecture for providing pipelined data paths 227 1997
2003/0154,349 Program-directed cache prefetching for media processors 49 2002
 
RICOH COMPANY, LTD. (6)
5,511,173 Programmable logic array and data processing unit using the same 110 1994
5,794,062 System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization 184 1995
5,854,918 Apparatus and method for self-timed algorithmic execution 108 1996
5,933,642 Compiling system and method for reconfigurable computing 146 1997
6,077,315 Compiling system and method for partially reconfigurable computing 98 1998
6,058,469 System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization 93 1998
 
PERFORMANCE SEMICONDUCTOR CORPORATION (1)
4,884,231 Microprocessor system with extended arithmetic logic unit 51 1986
 
NATIONAL SEMICONDUCTOR CORPORATION (3)
5,081,375 Method for operating a multiple page programmable logic device 101 1991
5,336,950 Configuration features in a configurable logic array 219 1993
5,784,636 Reconfigurable computer architecture for use in signal processing applications 279 1996
 
SNAP-ON TOOLS CORPORATION (1)
5,218,302 Interface for coupling an analyzer to a distributorless ignition system 62 1991
 
HTC CORPORATION (2)
5,706,482 Memory access controller 131 1996
6,219,833 Method of using primary and secondary processors 94 1998
 
PACT INFORMATIONSTECHNOLOGIE AG (2)
7,210,129 Method for translating programs for reconfigurable architectures 72 2001
2004/0015,899 Method for processing data 72 2001
 
Carlstedt Elektronik AB (1)
5,555,434 Computing device employing a reduction processor and implementing a declarative language 88 1994
 
PANASONIC EUROPE LTD. (1)
6,553,395 Reconfigurable processor devices 61 2001
 
NORTEL NETWORKS LIMITED (1)
4,873,666 Message FIFO buffer controller 70 1987
 
NCR Corporation (1)
6,665,758 Software sanity monitor 74 1999
 
TM PATENTS, L.P. (1)
5,123,109 Parallel processor including a processor array with plural data transfer arrangements including (1) a global router and (2) a proximate-neighbor transfer system 95 1990
 
MUTEX SOLUTIONS, LTD. (1)
6,282,701 System and method for monitoring and analyzing the execution of computer programs 347 1998
 
SRI INTERNATIONAL (1)
6,757,892 Method for determining an optimal partitioning of data among several memories 61 2000
 
VLSI TECHNOLOGY, INC. (1)
5,860,119 Data-packet fifo buffer system with end-of-packet flags 83 1996
 
ADELANTE TECHNOLOGIES B.V. (1)
6,044,030 FIFO unit with single pointer 54 1998
 
PIE DESIGNS SYSTEMS, INC. (1)
5,425,036 Method and apparatus for debugging reconfigurable emulation systems 262 1992
 
GE FANUC AUTOMATION NORTH AMERICA, INC. (2)
5,109,503 Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters 107 1989
5,142,469 Method for converting a programmable logic controller hardware configuration and corresponding control program for use on a first programmable logic controller to use on a second programmable logic controller 129 1990
 
SUMITOMO BANK OF NEW YORK TRUST COMPANY (1)
6,378,068 Suspend/resume capability for a protected mode microprocesser 189 1995
 
APPLIED MICRO CIRCUITS CORPORATION (1)
6,512,804 Apparatus and method for multiple serial data synchronization using channel-lock FIFO buffers optimized for jitter 53 1999
 
BSC ACQUISTION, INC. (1)
6,260,179 Cell arrangement evaluating method, storage medium storing cell arrangement evaluating program, cell arranging apparatus and method, and storage medium storing cell arranging program 171 1998
 
SEFTA TRUSTEES LIMITED (1)
5,497,498 Video processing module using a second programmable logic device which reconfigures a first programmable logic device for data transformation 310 1993
 
NORMAN, RICHARD S. (2)
5,801,715 Massively-parallel processor array with outputs from individual processors directly to an external device without involving other processors or a common physical carrier 92 1994
5,748,872 Direct replacement cell fault tolerant architecture 225 1996
 
ROCKWELL COLLINS, INC. (1)
6,374,286 Real time processor capable of concurrently running multiple independent JAVA machines 316 1998
 
MENTOR GRAPHICS CORPORATION (1)
5,649,176 Transition analysis and circuit resynthesis method and device for digital circuit modeling 149 1995
 
MENTOR GRAPHICS (HOLDING) LTD. (1)
5,754,827 Method and apparatus for performing fully visible tracing of an emulation 114 1995
 
BANK OF AMERICA, N.A. (4)
6,150,837 Enhanced field programmable gate array 169 1997
6,211,697 Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure 156 1999
6,975,138 Method and apparatus for universal program controlled bus architecture 42 2004
7,382,156 Method and apparatus for universal program controlled bus architecture 42 2005
 
SCHLUMBERGER TECHNOLOGIES, INC. (1)
4,882,687 Pixel processor 95 1986
 
SP-COMMERCIAL FLIGHT, INC., A DE CORP. (1)
4,791,603 Dynamically reconfigurable array logic 85 1986
 
Virginia Tech Intellectual Properties, Inc. (1)
5,828,858 Worm-hole run-time reconfigurable processor field programmable gate array (FPGA) 161 1996
 
The United States of America as represented by the Secretary of the Air Force (2)
5,694,602 Weighted system and method for spatial allocation of a parallel load 69 1996
2002/0045,952 High performance hybrid micro-computer 67 2001
 
I-CUBE, INC. (1)
5,960,200 System to transition an enterprise to a distributed infrastructure 296 1996
 
Alliant Computer Systems Corporation (1)
5,099,447 Blocked matrix multiplication for computers with hierarchical memory 72 1990
 
SGS-Thomson Microelectronics, Inc. (1)
5,128,559 Logic block for programmable logic devices 221 1991
 
THESEUS RESEARCH, INC. (1)
4,667,190 Two axis fast access memory 92 1983
 
SGS-Thomson Microelectronics Limited (1)
5,473,267 Programmable logic device with memory that can store routing data of logic data 165 1995
 
Analog Devices, Inc. (1)
5,619,720 Digital signal processor having link ports for point-to-point communication 58 1996
 
MAXTOR CORPORATION (1)
5,041,924 Removable and transportable hard disk subsystem 163 1988
 
Iowa State University Research Foundation, Inc. (1)
6,339,840 Apparatus and method for parallelizing legacy computer code 55 1997
 
THE JOHNS HOPKINS UNIVERSITY (1)
4,720,780 Memory-linked wavefront array processor 235 1985
 
KAWASAKI MICROELECTRONICS, INC. (1)
6,437,441 Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure 107 1998
 
PICOCHIP DESIGNS LIMITED (1)
2004/0078,548 Processor architecture 65 2003
 
ANALOGIC CORPORATION (1)
5,301,344 Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets 141 1991
 
PRASENDT INVESTMENTS, LLC (1)
5,475,583 Programmable control system including a logic module and a method for programming 97 1992
 
ARIX COMPUTER CORPORATION, 821 FOX LANE SAN JOSE, CALIFORNIA 95131 (1)
5,276,836 Data processing device with common memory connecting mechanism 76 1991
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (1)
5,581,731 Method and apparatus for managing video data for faster access by selectively caching video data 55 1994
 
SIMA, MIHAI (1)
2009/0193,384 SHIFT-ENABLED RECONFIGURABLE DEVICE 30 2009
 
HITACHI, LTD. (4)
5,072,178 Method and apparatus for testing logic circuitry by applying a logical test pattern 109 1990
5,537,601 Programmable digital signal processor for performing a plurality of signal processings 247 1994
5,784,630 Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory 65 1995
5,848,238 Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them 76 1997
 
APPLE INC. (1)
6,434,695 Computer operating system using compressed ROM image in RAM 144 1998
 
U.S. DEPARTMENT OF ENERGY (1)
7,873,811 Polymorphous computing fabric 30 2003
 
KABUSHIKI KAISHA TOSHIBA (6)
5,867,691 Synchronizing system between function blocks arranged in hierarchical structures and large scale integrated circuit using the same 98 1993
5,572,710 High speed logic simulation system using time division emulation suitable for large scale logic circuits 91 1993
5,717,890 Method for processing data by utilizing hierarchical cache memories and processing system with the hierarchiacal cache memories 36 1995
5,754,820 Microprocessor system with cache memory for eliminating unnecessary invalidation of cache data 73 1995
5,862,403 Continuous data server apparatus and data transfer scheme enabling multiple simultaneous data accesses 81 1996
6,587,939 Information processing apparatus provided with an optimized executable instruction extracting unit for extending compressed instructions 77 2000
 
BELL TELEPHONE LABORATORIES INCORPORATED, 600 MOUNTAIN AVE., MURRAY HILL, NJ 07974-2070 A CORP. OF NY (2)
4,590,583 Coin telephone measurement circuitry 58 1982
4,682,284 Queue administration method and apparatus 127 1984
 
RAYTHEON COMPANY (2)
4,972,314 Data flow signal processor method and apparatus 147 1988
5,386,518 Reconfigurable computer interface and method 71 1993
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (40)
4,594,682 Vector processing 82 1982
4,566,102 Parallel-shift error reconfiguration 116 1983
4,992,933 SIMD array processor with global instruction control and reprogrammable instruction decoders 153 1990
5,212,716 Data edge phase sorting circuits 65 1991
5,347,639 Self-parallelizing computer system and method 108 1991
5,493,663 Method and apparatus for predetermining pages for swapping from physical memory in accordance with the number of accesses 50 1992
5,590,345 Advanced parallel array processor(APAP) 183 1992
5,590,348 Status predictor for combined shifter-rotate/merge unit 71 1992
5,311,079 Low power, high performance PLA 61 1992
5,581,734 Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity 67 1993
5,794,059 N-dimensional modified hypercube 140 1994
5,513,366 Method and system for dynamically reconfiguring a register file in a vector processor 166 1994
5,475,856 Dynamic multi-mode parallel processing array 321 1994
5,584,013 Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache 66 1994
5,682,491 Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier 87 1994
5,659,785 Array processor communication architecture with broadcast processor instructions 61 1995
5,617,577 Advanced parallel array processor I/O connection 61 1995
5,483,620 Learning machine synapse processor system apparatus 89 1995
6,405,185 Massively parallel array processor 58 1995
5,625,836 SIMD/MIMD processing memory element (PME) 122 1995
* 5,652,529 Programmable array clock/reset resource 66 1995
5,646,544 System and method for dynamically reconfiguring a programmable gate array 295 1995
5,717,943 Advanced parallel array processor (APAP) 174 1995
5,713,037 Slide bus communication functions for SIMD/MIMD array processor 105 1995
5,754,871 Parallel processing system having asynchronous SIMD processing 109 1995
5,978,583 Method for resource control in parallel environments using program organization and run-time support 98 1995
5,737,565 System and method for diallocating stream from a stream buffer 86 1995
5,588,152 Advanced parallel processor including advanced support hardware 164 1995
5,745,734 Method and system for programming a gate array using a compressed configuration bit stream 204 1995
6,311,265 Apparatuses and methods for programming parallel computers 105 1996
5,617,547 Switch network extension of bus architecture 116 1996
6,785,826 Self power audit and control circuitry for microprocessor functional units 75 1996
5,734,921 Advanced parallel array processor computer package 131 1996
6,128,720 Distributed processing array with component processors performing customized interpretation of instructions 84 1997
6,321,298 Full cache coherency across multiple raid controllers 77 1999
6,054,873 Interconnect structure between heterogeneous core regions in a programmable array 204 1999
6,321,373 Method for resource control in parallel environments using program organization and run-time support 98 1999
6,542,844 Method and apparatus for tracing hardware states using dynamically reconfigurable test circuits 119 2000
6,829,697 Multiple logical interfaces to a shared coprocessor resource 85 2000
6,961,924 Displaying variable usage while debugging 71 2002
 
ADVANCED MICRO DEVICES, INC. (2)
5,625,806 Self configuring speed path in a microprocessor with multiple clock option 76 1996
6,298,396 System for loading a current buffer desciptor register with a value different from current value to cause a previously read buffer descriptor to be read again 53 1998
 
HIRANUMA, TAKEO (1)
6,188,240 Programmable function block 91 1999
 
LSI LOGIC CORPORATION (2)
5,475,803 Method for 2-D affine transformation of images 145 1992
5,801,958 Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information 281 1996
 
SIEMENS AKTIENGESELLSCHAFT (1)
5,043,978 Circuit arrangement for telecommunications exchanges 80 1989
 
FUJITSU LIMITED (6)
5,506,998 Parallel data processing system using a plurality of processing elements to process data and a plurality of trays connected to some of the processing elements to store and transfer data 100 1994
5,544,336 Parallel data processing system which efficiently performs matrix and neurocomputer operations, in a negligible data transmission time 94 1995
5,655,069 Apparatus having a plurality of programmable logic processing units for self-repair 168 1996
6,185,256 Signal transmission system using PRD method, receiver circuit for use in the signal transmission system, and semiconductor memory device to which the signal transmission system is applied 69 1998
6,404,224 Chain-connected shift register and programmable logic circuit whose logic function is changeable in real time 166 1999
2009/0085,603 FPGA configuration protection and control using hardware watchdog timer 45 2007
 
INFINEON TECHNOLOGIES AG (2)
6,717,436 Reconfigurable gate array 108 2002
7,254,649 Wireless spread spectrum communication platform using dynamically reconfigurable logic 60 2005
 
Deutsche ITT Industries GmbH (1)
5,410,723 Wavefront array processor for blocking the issuance of first handshake signal (req) by the presence of second handshake signal (ack) which indicates the readyness of the receiving cell 127 1993
 
ROUND ROCK RESEARCH, LLC (3)
5,247,689 Parallel digital processor including lateral transfer buses with interrupt switches to form bus interconnection segments 123 1990
5,887,162 Memory device having circuitry for initializing and reprogramming a control operation feature 71 1997
6,170,051 Apparatus and method for program level parallelism in a VLIW processor 143 1997
 
HOLOGIC, INC. (1)
6,430,309 Specimen preview and inspection system 68 1998
 
PRINCETON GAMMA-TECH INSTRUMENTS, INC. (1)
5,349,193 Highly sensitive nuclear spectrometer apparatus and method 90 1993
 
MZMZ Technology Innovations LLC (1)
6,260,114 Computer cache memory windowing 71 1997
 
FREESCALE SEMICONDUCTOR, INC. (3)
5,561,738 Data processor for executing a fuzzy logic operation and method therefor 95 1994
5,815,715 Method for designing a product having hardware and software components and product therefor 75 1995
5,737,516 Data processing system for performing a debug function and method therefor 157 1995
 
Altera Corporation (26)
5,444,394 PLD with selective inputs from local and global conductors 140 1993
5,550,782 Programmable logic array integrated circuits 291 1994
5,473,266 Programmable logic device having fast programmable logic array blocks and a central global interconnect array 115 1994
5,485,103 Programmable logic array with local and global conductors 188 1994
5,537,057 Programmable logic array device with grouped logic regions and three types of conductors 261 1995
5,570,040 Programmable logic array integrated circuit incorporating a first-in first-out memory 192 1995
5,541,530 Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks 153 1995
5,815,726 Coarse-grained look-up table architecture 223 1995
6,020,758 Partially reconfigurable programmable logic device 118 1996
5,859,544 Dynamic configurable elements for programmable logic devices 118 1996
5,828,229 Programmable logic array integrated circuits 158 1997
6,085,317 Reconfigurable computer architecture using programmable logic devices 171 1997
6,134,166 Programmable logic array integrated circuit incorporating a first-in first-out memory 55 1998
6,247,147 Enhanced embedded logic analyzer 108 1998
6,216,223 Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor 75 1999
6,215,326 Programmable logic device architecture with super-regions having logic regions and a memory region 226 1999
6,658,564 Reconfigurable programmable logic device computer system 98 1999
2001/0032,305 Methods and apparatus for dual-use coprocessing/debug interface 121 2001
7,340,596 Embedded processor with watchdog timer for programmable logic 56 2001
2002/0124,238 Software-to-hardware compiler 61 2001
6,538,470 Devices and methods with programmable logic and digital signal processing regions 210 2001
6,525,678 Configuring a programmable logic device 75 2001
7,000,161 Reconfigurable programmable logic system with configuration recovery mode 65 2002
7,350,178 Embedded processor with watchdog timer for programmable logic 52 2004
2006/0036,988 Methods and apparatus for implementing parameterizable processors and peripherals 37 2005
7,346,644 Devices and methods with programmable logic and digital signal processing regions 52 2006
 
CALIFORNIA INSTITUTE OF TECHNOLOGY (1)
6,038,656 Pipelined completion for asynchronous communication 88 1998
 
ELBRUS INTERNATIONAL LIMITED (1)
6,301,706 Compiler method and apparatus for elimination of redundant speculative computations from innermost loops 72 1998
 
MIRALFIN S.R.L. (1)
5,760,602 Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA 124 1996
 
MORPHO TECHNOLOGIES (1)
2003/0123,579 Viterbi convolutional coding method and apparatus 72 2002
 
ISCO, INC. (1)
5,125,801 Pumping system 81 1990
 
PRINCETON UNIVERSITY, NON-PROFIT ORGANIZATION (1)
4,811,214 Multinode reconfigurable pipeline computer 240 1986
 
KEYBOARD KOMFORT, INC. (1)
5,966,143 Data allocation into multiple memories for concurrent access 59 1997
 
Actel Corporation (5)
5,440,245 Logic module with configurable combinational and sequential blocks 103 1993
5,457,644 Field programmable digital signal processing array integrated circuit 176 1993
5,510,730 Reconfigurable programmable interconnect architecture 119 1995
5,600,265 Programmable interconnect architecture 119 1995
6,504,398 Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure 82 2000
 
MICROSOFT TECHNOLOGY LICENSING, LLC (3)
6,298,043 Communication system architecture and a connection verification mechanism therefor 87 1998
6,748,440 Flow of streaming data through multiple processing modules 52 1999
7,007,096 Efficient splitting and mixing of streaming-data frames for processing through multiple processing modules 57 1999
 
The Trustees of Princeton University (1)
5,442,790 Optimizing compiler for computers 177 1994
 
QUALCOMM INCORPORATED (1)
7,249,351 System and method for preparing software for execution in a dynamically configurable hardware environment 62 2000
 
NANOWIRE LIMITED LIABILITY COMPANY (1)
6,092,174 Dynamically reconfigurable distributed integrated circuit processor and method 139 1998
 
ALLEN-BRADLEY COMPANY, INC. (1)
5,428,526 Programmable controller with time periodic communication 80 1993
 
CVSI, INC. (1)
4,761,755 Data processing system and method having an improved arithmetic unit 106 1984
 
E-SYSTEMS, INC. (1)
4,967,340 Adaptive processing system having an array of individually configurable processing components 197 1988
 
BOBRICK WASHROOM EQUIPMENT, INC. (1)
4,489,857 Liquid dispenser 47 1982
 
France Telecom (1)
5,465,375 Multiprocessor system with cascaded modules combining processors through a programmable logic cell array 138 1993
 
VTECH INDUSTRIES, INC. (1)
5,696,791 Apparatus and method for decoding a sequence of digitally encoded data 45 1995
 
GENERAL DYNAMICS C4 SYSTEMS, INC. (1)
5,999,990 Communicator having reconfigurable resources 231 1998
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
CYPRESS SEMICONDUCTOR CORPORATION (3)
8,441,298 Analog bus sharing using transmission gates 2 2009
* 2011/0026,519 DYNAMICALLY RECONFIGURABLE ANALOG ROUTING CIRCUITS AND METHODS FOR SYSTEM ON A CHIP 2 2010
8,890,600 Bus sharing scheme 0 2013
 
INTEL CORPORATION (1)
* 2012/0169,746 METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING NON FRAME AWARE FREQUENCY SELECTION 0 2011
* Cited By Examiner

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
3.5 Year Payment $1600.00 $800.00 $400.00 Jul 17, 2015
7.5 Year Payment $3600.00 $1800.00 $900.00 Jul 17, 2019
11.5 Year Payment $7400.00 $3700.00 $1850.00 Jul 17, 2023
Fee Large entity fee small entity fee micro entity fee
Surcharge - 3.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge - 7.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00