
US Patent No: 8,099,618
Number of patents in Portfolio can not be more than 2000
Methods and devices for treating and processing data
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Jan 17, 2012
Issued date -
Oct 23, 2008
filing date -
12/257,075
serial no -
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status
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Abstract
A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.
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First Claim
Related Publications
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 5,867,691 Synchronizing system between function blocks arranged in hierarchical structures and large scale integrated circuit using the same | 77 | 1993 | |
| 5,572,710 High speed logic simulation system using time division emulation suitable for large scale logic circuits | 71 | 1993 | |
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| 5,754,820 Microprocessor system with cache memory for eliminating unnecessary invalidation of cache data | 56 | 1995 | |
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| 6,587,939 Information processing apparatus provided with an optimized executable instruction extracting unit for extending compressed instructions | 59 | 2000 | |
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| 5,511,173 Programmable logic array and data processing unit using the same | 92 | 1994 | |
| 5,794,062 System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization | 147 | 1995 | |
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| 5,933,642 Compiling system and method for reconfigurable computing | 111 | 1997 | |
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| 6,058,469 System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization | 69 | 1998 | |
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| 6,256,724 Digital signal processor with efficiently connectable hardware co-processor | 45 | 1999 | |
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| 6,598,128 Microprocessor having improved memory management unit and cache memory | 32 | 1999 | |
| 6,400,601 Nonvolatile semiconductor memory device | 49 | 2000 | |
| 2010/0306,602 SEMICONDUCTOR DEVICE AND ABNORMALITY DETECTING METHOD | 17 | 2010 | |
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| 5,144,166 Programmable logic cell and array | 322 | 1990 | |
| 5,894,565 Field programmable gate array with distributed RAM and increased cell utilization | 89 | 1996 | |
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| 6,687,788 Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.) | 50 | 2002 | |
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| 5,600,845 Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor | 167 | 1994 | |
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Patent Citation Ranking
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