Chip package structure and method for fabricating the same
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United States of America Patent
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Jan 24, 2012
Grant Date -
May 12, 2011
app pub date -
Mar 26, 2010
filing date -
Nov 12, 2009
priority date (Note) -
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status (Latency Note)
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Abstract
The disclosure provides a chip package structure and method for fabricating the same. The chip package structure includes at least one chip having at least one through via. At least one stress buffering structure is disposed in the through via. The stress buffering structure includes a first gasket and a second gasket. A supporting pillar has two terminals respectively connected to the first gasket and the second gasket. The cross-sectional area of the supporting pillar is smaller than areas of the first gasket and the second gasket. A buffering layer is sandwiched between the first gasket and the second gasket, surrounding a sidewall of the supporting pillar. An insulating layer is disposed on the through via, surrounding a sidewall of the stress buffering structure.
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