Linking functional blocks for sequential operation by DONE and GO components of respective blocks pointing to same memory location to store completion indicator read as start indicator
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United States of America Patent
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Jan 24, 2012
Grant Date -
Mar 26, 2009
app pub date -
Jun 29, 2008
filing date -
Sep 22, 2007
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Abstract
The present disclosure provides a methodology for reducing congestion of a processing unit, preferably by configuring a plurality of functional blocks to run in parallel or in series without the influence or input from the processing unit. In an embodiment, the present method chains a plurality of functional blocks together by software so that one functional block starts after the completion of another functional block. The configuration of the chain can be series, parallel, and any combination thereof, arranged to meet the circuit's objective. The chaining can be configured and re-configured, preferably by software input. The chaining can also be performed at design time or at run time. The chaining can also be modified, preferably at design time, but can also be modified at run time.
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| NAVOSHA CORPORATION | SUNNYVALE CA |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Kulkarni, Raj | Sunnyvale, US | 4 | 27 |
| Mitra, Hirak | Sunnyvale, US | 13 | 61 |
| Moon, Michael | Sunnyvale, US | 11 | 167 |
| Wicks, Richard | Sunnyvale, US | 5 | 36 |
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| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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