Importance

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Abstract

A delay locked loop (DLL) circuit includes a clock input buffer that generates a reference clock signal by buffering an external clock signal and outputs the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal. The DLL circuit also includes a timing compensation unit configured that generates a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during the duty cycle correction operation in response to a timing control signal. The DLL circuit further includes and a duty cycle control unit that generates the duty cycle control signal and the timing control signal by detecting the duty cycle of the reference clock signal.

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First Claim