System for minimizing the power consumption of a device in a power down mode

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United States of America Patent

PATENT NO 8108695
APP PUB NO 20090295468A1
SERIAL NO

12154913

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Abstract

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A system is disclosed for reducing power drain of a component when the component is in a powered down state. The system comprises a power input configured to receive power, a power output to the component, monitor logic configured to monitor a level of power moving between the input and output, and control logic configured to control power transfer between the input and output. The control logic may be in communication with the monitor logic and configured to selectively restrict power flow between the input and output when the monitor logic senses that power flow between the input and output falls below a threshold level. A method comprises checking a power level between the input and output, and if the power level exceeds a threshold, then permitting substantially unrestricted power flow. If the power level is less than the threshold, then restricting the power level between the input and output.

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Patent Owner(s)

Patent OwnerAddress
GATEWAY INC14303 GATEWAY PLACE POWAY CA 92064

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Love, John Sioux City, US 30 590

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