Optimal channel design for memory devices for providing a high-speed memory interface
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United States of America Patent
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Feb 7, 2012
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N/A
app pub date -
Nov 16, 2007
filing date -
Nov 16, 2007
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Abstract
A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communication between the memory controller and the plurality of memory devices, an impedance of the channel being at least partially controlled using High Density Interconnect (HDI) technology.
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