Microelectronic assemblies having compliancy and methods therefor
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United States of America Patent
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Feb 14, 2012
Grant Date -
Sep 16, 2010
app pub date -
May 21, 2010
filing date -
Dec 20, 2006
priority date (Note) -
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Abstract
A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.
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