Method and apparatus for efficient ordered stores over an interconnection network

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United States of America Patent

PATENT NO 8117392
APP PUB NO 20050091121A1
SERIAL NO

10691176

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Abstract

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A physically distributed cache memory system includes an interconnection network, first level cache memory slices, and second level cache memory slices. The first level cache memory slices are coupled to the interconnection network to generate tagged ordered store requests. Each tagged ordered store requests has a tag including requester identification and a store sequence token. The second level cache memory slices are coupled to the interconnection network to execute ordered store requests in-order across the physically distributed cache memory system in response to each tag of the tagged ordered store requests.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BLVD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ahuja, Pritpal S Waltham, US 6 27
Charney, Mark J Lexington, US 200 2089
Mattina, Matthew C Worcester, US 5 73
Rajwar, Ravi Portland, US 85 2381

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