Method and system of error logging
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United States of America Patent
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Feb 21, 2012
Grant Date -
Jul 21, 2011
app pub date -
Jan 21, 2010
filing date -
Jan 21, 2010
priority date (Note) -
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status (Latency Note)
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Abstract
Method and system of error logging. At least some of the illustrative embodiments are methods including detecting assertion of an error pin by a processor system, (comprising at least a main processor and a chipset, the assertion of the error pin an indication to reboot the processor system) the detecting by a reset circuit, notifying a management processor (distinct from the main processor) that the error pin is asserted (the notifying by the reset circuit), writing to a plurality of registers in the chipset (the writing by the management processor), de-asserting a reset pin of the main processor, and then executing by the main processor an error-handling code to generate an error log.
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