Method and apparatus for processing failures during semiconductor device testing
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United States of America Patent
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Feb 21, 2012
Grant Date -
Sep 17, 2009
app pub date -
Mar 11, 2008
filing date -
Mar 11, 2008
priority date (Note) -
Expired
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Abstract
Methods and apparatus for processing failures during semiconductor device testing are described. Examples of the invention can relate to testing a device under test (DUT). Fail capture logic can be provided, coupled to test probes and memory, to indicate only first failures of failures detected on output pins of the DUT during a test for storage in the memory.
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