Method for dicing a semiconductor wafer, a chip diced from a semiconductor wafer, and an array of chips diced from a semiconductor wafer
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United States of America Patent
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Mar 6, 2012
Grant Date -
Jun 23, 2011
app pub date -
Dec 23, 2009
filing date -
Dec 23, 2009
priority date (Note) -
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Abstract
A method for dicing a semiconductor wafer, including: cutting a reference slot in a back main surface of the wafer; cutting a back slot in the back main surface, the back slot positioned with respect to the reference slot; determining a desired location for a chip edge with respect to the reference slot; and applying radiant energy in a path such that a series of reformed regions are formed within the wafer along the path. A crystalline structure of the wafer is modified in the series of reformed regions and an alignment of an edge of the laser is with respect to the desired location for the chip edge and in alignment with the back slot. The method includes separating the wafer along the series of reformed regions to divide portions of the wafer on either side of the series of reformed regions.
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