Materials, structures and methods for microelectronic packaging

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United States of America Patent

PATENT NO 8129823
SERIAL NO

11986998

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Abstract

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Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CALIFORNIA 95054 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Tanikella, Ravindra V Phoenix, US 9 67

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