Multi-rank partial width memory modules
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United States of America Patent
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Mar 6, 2012
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N/A
app pub date -
Nov 13, 2007
filing date -
Nov 13, 2006
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Abstract
A system is provided for multi-rank, partial-width memory modules. A memory controller is provided. Additionally, a memory bus is provided. Further, a memory module with a plurality of ranks of memory circuits is provided, the memory module including a first number of data pins that is less than a second number of data pins of the memory bus.
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