Method and apparatus for improving throughput on a common bus
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United States of America Patent
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Mar 13, 2012
Grant Date -
N/A
app pub date -
Apr 7, 2008
filing date -
Apr 7, 2008
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A bus scheduling device having a group of direct memory access (“DMA”) engines, a group of target modules (“TM”), a read pending memory, and a bus arbiter is disclosed. A common bus, which is coupled with the DMA engines, TMs, and the read pending memory, is employed in the device for data transmission. DMA engines are capable of transmitting and receiving data to and from TMs via the common bus. The read pending memory is capable of storing information indicating the read status of the DMA engines. The arbiter or bus arbiter arbitrates bus access in response to a bus allocation scheme and the information stored in the read pending memory.
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