Wafer level integrated interconnect decal and manufacturing method thereof
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United States of America Patent
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Mar 20, 2012
Grant Date -
Sep 29, 2011
app pub date -
Mar 25, 2010
filing date -
Mar 25, 2010
priority date (Note) -
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Abstract
A wafer level integrated interconnect decal manufacturing method and wafer level integrated interconnect decal arrangement. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps.
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