Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same
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United States of America Patent
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Mar 20, 2012
Grant Date -
Nov 25, 2010
app pub date -
Aug 4, 2010
filing date -
Nov 20, 2006
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Abstract
In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.
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