Mixed data rates in memory devices and systems
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United States of America Patent
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Mar 20, 2012
Grant Date -
Jan 14, 2010
app pub date -
Jul 8, 2008
filing date -
Jul 8, 2008
priority date (Note) -
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Abstract
Mixed data rates in a memory system is disclosed. The system includes at least one semiconductor memory device and another device defining a ring topology. The semiconductor memory device includes input circuitry for receiving a clock signal having a frequency at least substantially equal to a frequency x. A first set of circuit elements are each clocked by a same or respective first internal signal having a frequency at least substantially equal to the frequency x. A second set of circuit elements are each clocked by a same or a respective second internal signal having a frequency at least substantially double that of the frequency x.
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