Power-on initialization and test for a cascade interconnect memory system
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United States of America Patent
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Mar 20, 2012
Grant Date -
Jan 7, 2010
app pub date -
Jul 1, 2008
filing date -
Jul 1, 2008
priority date (Note) -
Expired
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Abstract
A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
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