System for data processing using a multi-tiered full-graph interconnect architecture
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United States of America Patent
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Mar 20, 2012
Grant Date -
Mar 5, 2009
app pub date -
Aug 27, 2007
filing date -
Aug 27, 2007
priority date (Note) -
Expired
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Abstract
A system is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.
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