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Abstract

A memory component includes a memory core, a control transport block to receive a write command from external control lines, and a write control buffer to store the write command for a first time period after the write command is received at the transport block. A data buffer receives data from external data lines, the data to be stored in the memory core in response to the write command, wherein receipt of the data occurs based on a second time period that follows the first time period, such that receipt of the write command and the data are separated by a delay time that includes both the first time period and the second time period. A write mask buffer receives write masking information from an external write mask line. Receipt of the write command and the write masking information are separated by the delay time.

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First Claim