Sequential fabrication of vertical conductive interconnects in capped chips
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United States of America Patent
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Mar 27, 2012
Issued Date -
N/A
app pub date -
Dec 28, 2005
filing date -
Mar 22, 2005
priority date (Note) -
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Abstract
A method is provided of forming a capped chip which includes a conductive interconnect exposed through an opening in the cap. A cap having openings extending between outer and inner surfaces is aligned and joined to a chip. A mass of fusible conductive material is positioned through a first such opening onto a first such bond pad of the chip. The positioned mass is heated to bond the mass to the first bond pad. The steps of positioning and heating the mass form at least a portion of a conductive interconnect extending from the first bond pad at least partially through the first opening.
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