Method of fabricating extended drain MOS transistor

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United States of America Patent

PATENT NO 8143139
APP PUB NO 20090057785A1
SERIAL NO

12197331

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Abstract

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A method of fabricating an extended drain MOS transistor which reduces a design rule and prevents the generation of leakage current. The method includes sequentially forming a diffusion film, a first conductive epitaxial layer, a gate oxide layer and a hard mask layer over a semiconductor substrate, forming a first hard mask pattern having a first thickness by performing a first etching process on the hard mask layer, forming a second hard mask pattern having a second thickness by performing a second etching process on the first hard mask layer, and then forming a thin gate oxide layer by performing a third etching process on the gate oxide layer using the second hard mask pattern as a mask.

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Patent Owner(s)

Patent OwnerAddress
DONGBU HITEK CO LTDSEOUL CITY KOREA SEOUL

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lee, Kyoung-Jin Bucheon-si, KR 12 65

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