Test circuit for measuring resistance distribution of memory cells and semiconductor system including the same
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United States of America Patent
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Mar 27, 2012
Grant Date -
Apr 8, 2010
app pub date -
Oct 7, 2009
filing date -
Oct 8, 2008
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Abstract
The test circuit for measuring a resistance distribution of memory cells includes a sensing circuit and a digital value generation circuit. The sensing circuit compares a reference voltage with a voltage of a sensing node receiving a voltage of a bit line connected with a resistive element and generates a sensing signal. The digital value generation circuit generates a digital value corresponding to a resistance-capacitance (RC) delay of the bit line in response to the sensing signal from the sensing circuit.
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