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Abstract

A reconfigurable computing apparatus includes plural computing element networks respectively formed of computing elements of an identical bit width, the bit width of each of the computing element networks differing according to computing element network; a bit width converting element that converts bit widths between the computing element networks; a control signal-dedicated network that is formed of computing elements, is reconfigurable, and controls each of the computing element networks; and a sequencer that controls a timing at which circuit configurations are switched with respect to the computing element networks, the control signal-dedicated network, and the bit width converting element.

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