US Patent No: 8,154,935

Number of patents in Portfolio can not be more than 2000

Delaying a signal communicated from a system to at least one of a plurality of memory circuits

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ALSO PUBLISHED AS: 20100271888
ATTORNEY / AGENT: (SPONSORED)
 

Importance

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Abstract

A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
GOOGLE INC.MOUNTAIN VIEW, CA6665

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rajan, Suresh Natarajan San Jose, CA 95 1779
Schakel, Keith R San Jose, CA 80 1714
Smith, Michael John Sebastian Palo Alto, CA 87 1700
Wang, David T San Jose, CA 109 1926
Weber, Frederick Daniel San Jose, CA 70 1559

Cited Art

Patent Info (Count) # Cites Year
 
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5,526,320 Burst EDO memory device 143 1994
5,610,864 Burst EDO memory device with maximized write cycle timing 89 1995
5,652,724 Burst EDO memory device having pipelined output buffer 87 1995
5,675,549 Burst EDO memory device address counter 77 1995
5,598,376 Distributed write data drivers for burst access memories 110 1995
5,729,503 Address transition detection on a synchronous design 73 1995
5,724,288 Data communication for memory 39 1995
5,668,773 Synchronous burst extended data out DRAM 70 1995
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5,721,859 Counter control circuit in a burst memory 68 1995
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5,627,791 Multiple bank memory with auto refresh to specified bank 188 1996
5,661,695 Burst EDO memory device 60 1996
5,802,010 Burst EDO memory device 53 1996
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5,703,813 DRAM having multiple column address strobe operation 46 1996
5,696,732 Burst EDO memory device 54 1996
5,706,247 Self-enabling pulse-trapping circuit 54 1996
5,949,254 Adjustable output driver circuit 100 1996
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5,870,347 Multi-bank memory input/output line selection 82 1997
5,875,142 Integrated circuit with temperature detector 79 1997
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5,946,265 Continuous burst EDO memory device 67 1997
5,831,932 Self-enabling pulse-trapping circuit 46 1997
5,850,368 Burst EDO memory address counter 55 1997
6,002,613 Data communication for memory 37 1997
5,963,504 Address transition detection in a synchronous design 62 1997
6,016,282 Clock vernier adjustment 216 1998
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6,084,434 Adjustable output driver circuit 49 1999
6,453,402 Method for synchronizing strobe and data signals from a RAM 54 1999
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7,120,727 Reconfigurable memory module and method 113 2003
7,428,644 System and method for selective memory module power management 44 2003
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6,862,202 Low power memory module using restricted device activation 35 2003
2006/0041,730 Memory command delay balancing in a daisy-chained memory topology 50 2004
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7,277,333 Power savings in active standby mode 32 2005
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GOOGLE INC. (65)
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7,609,567 System and method for simulating an aspect of a memory circuit 35 2006
7,724,589 System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits 31 2006
2008/0025,108 SYSTEM AND METHOD FOR DELAYING A SIGNAL COMMUNICATED FROM A SYSTEM TO AT LEAST ONE OF A PLURALITY OF MEMORY CIRCUITS 35 2006
2008/0025,122 MEMORY REFRESH SYSTEM AND METHOD 32 2006
2008/0025,136 SYSTEM AND METHOD FOR STORING AT LEAST A PORTION OF INFORMATION RECEIVED IN ASSOCIATION WITH A FIRST OPERATION FOR USE IN PERFORMING A SECOND OPERATION 35 2006
2008/0025,137 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 35 2006
2008/0027,702 SYSTEM AND METHOD FOR SIMULATING A DIFFERENT NUMBER OF MEMORY CIRCUITS 35 2006
2008/0028,135 MULTIPLE-COMPONENT MEMORY INTERFACE SYSTEM AND METHOD 34 2006
2008/0031,072 POWER SAVING SYSTEM AND METHOD FOR USE WITH A PLURALITY OF MEMORY CIRCUITS 31 2006
7,379,316 Methods and apparatus of stacking DRAMs 55 2006
2007/0058,471 Methods and apparatus of stacking DRAMs 42 2006
7,386,656 Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit 38 2006
7,392,338 Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits 35 2006
7,472,220 Interface circuit system and method for performing power management operations utilizing power management signals 35 2006
7,590,796 System and method for power management in memory systems 33 2006
2008/0031,030 System and method for power management in memory systems 49 2006
2008/0082,763 APPARATUS AND METHOD FOR POWER MANAGEMENT OF MEMORY CIRCUITS BY A SYSTEM OR COMPONENT THEREOF 32 2006
7,581,127 Interface circuit system and method for performing power saving operations during a command-related latency 33 2006
2008/0037,353 Interface circuit system and method for performing power saving operations during a command-related latency 31 2006
2008/0027,697 MEMORY CIRCUIT SIMULATION SYSTEM AND METHOD WITH POWER SAVING CAPABILITIES 31 2006
2008/0027,703 MEMORY CIRCUIT SIMULATION SYSTEM AND METHOD WITH REFRESH CAPABILITIES 31 2006
2008/0123,459 COMBINED SIGNAL DELAY AND POWER SAVING SYSTEM AND METHOD FOR USE WITH A PLURALITY OF MEMORY CIRCUITS 31 2006
2008/0086,588 System and Method for Increasing Capacity, Performance, and Flexibility of Flash Storage 38 2006
2007/0195,613 Memory module with memory stack and interface with enhanced capabilities 52 2007
2008/0126,690 Memory module with memory stack 48 2007
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2007/0204,075 SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS 38 2007
2008/0056,014 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 35 2007
2008/0062,773 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 35 2007
2008/0010,435 MEMORY SYSTEMS AND MEMORY MODULES 43 2007
2008/0028,136 METHOD AND APPARATUS FOR REFRESH MANAGEMENT OF MEMORY MODULES 31 2007
2008/0028,137 Method and Apparatus For Refresh Management of Memory Modules 33 2007
2008/0103,753 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 35 2007
2008/0104,314 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 33 2007
2008/0109,206 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 33 2007
2008/0109,595 SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS 36 2007
2008/0109,597 METHOD AND APPARATUS FOR REFRESH MANAGEMENT OF MEMORY MODULES 33 2007
2008/0109,598 Method and apparatus for refresh management of memory modules 33 2007
2008/0120,443 SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS 34 2007
2008/0126,687 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 33 2007
2008/0126,688 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 33 2007
2008/0126,689 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 33 2007
2008/0126,692 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 33 2007
2008/0133,825 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 33 2007
2009/0024,789 MEMORY CIRCUIT SYSTEM AND METHOD 36 2007
2009/0024,790 MEMORY CIRCUIT SYSTEM AND METHOD 33 2007
2008/0115,006 SYSTEM AND METHOD FOR ADJUSTING THE TIMING OF SIGNALS ASSOCIATED WITH A MEMORY SYSTEM 43 2007
7,599,205 Methods and apparatus of stacking DRAMs 36 2008
2008/0170,425 METHODS AND APPARATUS OF STACKING DRAMS 51 2008
7,730,338 Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits 31 2008
7,761,724 Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit 31 2008
2008/0239,857 INTERFACE CIRCUIT SYSTEM AND METHOD FOR PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH ONLY A PORTION OF A MEMORY CIRCUIT 31 2008
2008/0239,858 INTERFACE CIRCUIT SYSTEM AND METHOD FOR AUTONOMOUSLY PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH A PLURALITY OF MEMORY CIRCUITS 31 2008
2009/0216,939 Emulation of abstracted DIMMs using abstracted DRAMs 31 2009
2009/0285,031 SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT 31 2009
2009/0290,442 METHOD AND CIRCUIT FOR CONFIGURING MEMORY CORE INTEGRATED CIRCUIT DIES WITH MEMORY INTERFACE INTEGRATED CIRCUIT DIES 31 2009
2010/0020,585 METHODS AND APPARATUS OF STACKING DRAMS 31 2009
2010/0271,888 System and Method for Delaying a Signal Communicated from a System to at Least One of a Plurality of Memory Circuits 32 2010
2010/0257,304 APPARATUS AND METHOD FOR POWER MANAGEMENT OF MEMORY CIRCUITS BY A SYSTEM OR COMPONENT THEREOF 33 2010
2010/0281,280 Interface Circuit System And Method For Performing Power Management Operations In Conjunction With Only A Portion Of A Memory Circuit 31 2010
 
INTEL CORPORATION (47)
5,388,265 Method and apparatus for placing an integrated circuit chip in a reduced power consumption state 153 1993
5,860,106 Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem 120 1995
5,692,202 System, apparatus, and method for managing power in a computer system 65 1995
6,279,069 Interface for flash EEPROM memory arrays 224 1996
5,903,500 1.8 volt output buffer on flash memories 48 1997
5,884,088 System, apparatus and method for managing power in a computer system 69 1997
5,835,435 Method and apparatus for dynamically placing portions of a memory in a reduced power consumtion state 80 1997
6,298,426 Controller configurable for use with multiple memory organizations 76 1997
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6,587,912 Method and apparatus for implementing multiple memory buses on a memory module 254 1998
6,038,673 Computer system with power management scheme for DRAM devices 55 1998
6,442,698 Method and apparatus for power management in a memory subsystem 63 1998
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6,356,105 Impedance control system for a center tapped termination bus 71 2000
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6,487,102 Memory module having buffer for isolating stacked memory devices 138 2000
6,553,450 Buffer to multiply memory interface 137 2000
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6,862,653 System and method for controlling data flow direction in a memory system 38 2000
6,618,791 System and method for controlling power states of a memory device via detection of a chip select signal 55 2000
6,742,098 Dual-port buffer-to-memory interface 119 2000
6,785,767 Hybrid mass storage system and method with two different types of storage medium 65 2000
6,563,337 Driver impedance control mechanism 48 2001
6,820,169 Memory control with lookahead power management 46 2001
2003/0105,932 Emulation of memory clock enable pin and use of chip select for memory power control 44 2001
6,714,891 Method and apparatus for thermal management of a power supply to a high performance processor in a computer system 52 2001
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7,024,518 Dual-port buffer-to-memory interface 55 2002
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2003/0183,934 Method and apparatus for stacking multiple die in a flip chip semiconductor package 39 2002
7,103,730 Method, system, and apparatus for reducing power consumption of a memory 58 2002
6,639,820 Memory buffer arrangement 50 2002
6,747,887 Memory module having buffer for isolating stacked memory devices 49 2002
6,839,290 Method, apparatus, and system for high speed data transfer using source synchronous data strobe 38 2003
2005/0108,460 Partial bank DRAM refresh 41 2003
7,127,567 Performing memory RAS operations over a point-to-point interconnect 34 2003
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6,075,730 High performance cost optimized memory with delayed memory writes 93 1998
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6,701,446 Power control system for synchronous memory device 72 2001
6,493,789 Memory device which receives write masking and automatic precharge information 79 2001
6,564,281 Synchronous memory device having automatic precharge 39 2001
6,546,446 Synchronous memory device having automatic precharge 35 2001
6,807,598 Integrated circuit device having double data rate capability 42 2002
6,597,616 DRAM core refresh with reduced spike current 34 2002
6,584,037 Memory device which samples data after an amount of time transpires 59 2002
7,043,599 Dynamic memory supporting simultaneous refresh and data-access transactions 61 2002
7,363,422 Configurable width buffered module 43 2004
7,269,708 Memory controller for non-homogenous memory system 44 2004
7,003,639 Memory controller with power management logic 45 2004
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2007/0088,995 SYSTEM INCLUDING A BUFFERED MEMORY MODULE 55 2006
 
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5,563,086 Integrated memory cube, structure and fabrication 88 1995
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5,590,071 Method and apparatus for emulating a high capacity DRAM 57 1995
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5,692,121 Recovery unit for mirrored processors 59 1996
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5,963,464 Stackable memory card 94 1998
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6,381,668 Address mapping for system memory 67 1998
6,327,664 Power management on a memory card having a signal processing element 45 1999
6,453,434 Dynamically-tunable memory controller 41 2001
6,490,161 Peripheral land grid array package with improved thermal performance 69 2002
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7,480,774 Method for performing a command cancel function in a DRAM 34 2003
7,224,595 276-Pin buffered memory module with enhanced fault tolerance 83 2004
7,539,800 System, method and storage medium for providing segment level sparing 35 2004
2007/0106,860 REDISTRIBUTION OF MEMORY TO REDUCE COMPUTER SYSTEM POWER CONSUMPTION 59 2005
7,366,947 High reliability memory module with a fault tolerant address and command bus 35 2006
2008/0098,277 HIGH DENSITY HIGH RELIABILITY MEMORY MODULE WITH POWER GATING AND A FAULT TOLERANT ADDRESS AND COMMAND BUS 39 2006
2010/0005,218 ENHANCED CASCADE INTERCONNECTED MEMORY SYSTEM 33 2008
 
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6,208,168 Output driver circuits having programmable pull-up and pull-down capability for driving variable loads 49 1998
6,034,916 Data masking circuits and methods for integrated circuit memory devices, including data strobe signal synchronization 71 1998
6,526,473 Memory module system for controlling data input and output by connecting selected memory modules to a data line 54 1999
6,381,188 DRAM capable of selectively performing self-refresh operation for memory bank 56 2000
6,262,938 Synchronous DRAM having posted CAS latency and method for controlling CAS latency 60 2000
6,362,656 Integrated circuit memory devices having programmable output driver circuits therein 48 2001
6,452,826 Memory module system 96 2001
6,498,766 Integrated circuit memory devices that utilize indication signals to increase reliability of reading and writing operations and methods of operating same 58 2001
6,459,651 Semiconductor memory device having data masking pin and memory system including the same 44 2001
6,590,822 System and method for performing partial array self-refresh operation in a semiconductor memory device 62 2001
6,560,158 Power down voltage control method and apparatus 47 2001
6,754,132 Devices and methods for controlling active termination resistors in a memory system 52 2002
6,762,948 Semiconductor memory device having first and second memory architecture and memory system using the same 43 2002
6,819,602 Multimode data buffer and method for controlling propagation delay time 48 2002
6,650,594 Device and method for selecting power down exit 64 2002
7,058,776 Asynchronous memory using source synchronous transfer and system employing the same 44 2003
6,819,617 System and method for performing partial array self-refresh operation in a semiconductor memory device 46 2003
7,215,561 Semiconductor memory system having multiple system data buses 38 2003
2004/0250,989 Clothespin type heat dissipating apparatus for semiconductor module 45 2004
6,862,249 Devices and methods for controlling active termination resistors in a memory system 37 2004
2004/0196,732 Multi-stage output multiplexing circuits and methods for double data rate synchronous memory devices 40 2004
6,878,570 Thin stacked package and manufacturing method thereof 36 2004
2005/0269,715 Semiconductor package, mold used in manufacturing the same, and method for manufacturing the same 29 2005
2005/0224,948 Semiconductor device package having buffered memory module and method thereof 36 2005
 
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5,661,677 Circuit and method for on-board programming of PRD Serial EEPROMS 101 1996
5,901,105 Dynamic random access memory having decoding circuitry for partial memory blocks 87 1997
5,859,792 Circuit for on-board programming of PRD serial EEPROMs 46 1997
5,963,463 Method for on-board programming of PRD serial EEPROMS 50 1997
6,111,812 Method and apparatus for adjusting control signal timing in a memory device 68 1999
6,317,381 Method and system for adaptively adjusting control signal timing in a memory device 51 1999
6,304,511 Method and apparatus for adjusting control signal timing in a memory device 47 2000
6,243,282 Apparatus for on-board programming of serial EEPROMs 41 2000
6,731,527 Architecture for a semiconductor memory device for minimizing interference and cross-coupling between control signal lines and power lines 38 2001
6,912,778 Methods of fabricating full-wafer silicon probe cards for burn-in and testing of semiconductor devices 42 2001
6,418,034 Stacked printed circuit board memory module and method of augmenting memory therein 45 2001
6,771,526 Method and apparatus for data transfer 45 2002
6,951,982 Packaged microelectronic component assemblies 73 2002
6,847,582 Low skew clock input buffer and method 57 2003
2006/0010,339 Memory system and method having selective ECC during low power refresh 66 2004
7,149,145 Delay stage-interweaved analog DLL/PLL 39 2004
6,943,450 Packaged microelectronic devices and methods of forming same 40 2004
6,947,341 Integrated semiconductor memory chip with presence detect data capability 35 2004
7,573,136 Semiconductor device assemblies and packages including multiple semiconductor device components 32 2005
2008/0195,894 Memory array error correction apparatus, systems, and methods 31 2007
 
QIMONDA AG (14)
6,526,484 Methods and apparatus for reordering of the memory requests to achieve higher average utilization of the command and data bus 50 1999
6,438,057 DRAM refresh timing adjustment device, system and method 97 2001
6,614,700 Circuit configuration with a memory array 36 2002
7,028,234 Method of self-repairing dynamic random access memory 38 2002
7,035,150 Memory device with column select being variably delayed 42 2002
6,986,118 Method for controlling semiconductor chips and control apparatus 40 2003
7,231,562 Memory module, test system and method for testing one or a plurality of memory modules 83 2004
6,894,933 Buffer amplifier architecture for semiconductor memory circuits 42 2004
7,061,784 Semiconductor memory module 43 2004
7,200,021 Stacked DRAM memory chip for a dual inline memory module (DIMM) 78 2004
7,266,639 Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM) 52 2004
7,079,441 Methods and apparatus for implementing a power down in a memory device 41 2005
7,414,917 Re-driving CAwD and rD signal lines 28 2005
2009/0109,613 MEMORY MODULE HEAT SINK 32 2007
 
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6,650,588 Semiconductor memory module and register buffer device for use in the same 43 2002
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HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (12)
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6,389,514 Method and computer system for speculatively closing pages in memory 118 1999
6,766,469 Hot-replace of memory 62 2001
2002/0002,662 Method and apparatus for supporting heterogeneous memory in computer systems 35 2001
6,684,292 Memory module resync 55 2001
6,665,227 Method and apparatus for reducing average power in RAMs by dynamically changing the bias on PFETs contained in memory cells 40 2001
7,028,215 Hot mirroring in a computer system with redundant memory subsystems 37 2002
6,659,512 Integrated circuit package employing flip-chip technology and method of assembly 34 2002
7,234,081 Memory module with testing logic 36 2004
2006/0236,165 Managing memory health 42 2005
 
MOSAID TECHNOLOGIES INCORPORATED (11)
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2002/0143,320 Tracking medical products with integrated circuits 2002
2002/0143,320 Tracking medical products with integrated circuits 2002
2002/0143,320 Tracking medical products with integrated circuits 2002
2002/0143,320 Tracking medical products with integrated circuits 2002
2002/0143,320 Tracking medical products with integrated circuits 2002
2002/0143,320 Tracking medical products with integrated circuits 2002
2002/0143,320 Tracking medical products with integrated circuits 2002
2002/0143,320 Tracking medical products with integrated circuits 2002
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2009/0132,648 CONTENT DELIVERY AND GLOBAL TRAFFIC MANAGEMENT NETWORK SYSTEM 2009
2009/0132,648 CONTENT DELIVERY AND GLOBAL TRAFFIC MANAGEMENT NETWORK SYSTEM 2009
2009/0132,648 CONTENT DELIVERY AND GLOBAL TRAFFIC MANAGEMENT NETWORK SYSTEM 2009
2009/0132,648 CONTENT DELIVERY AND GLOBAL TRAFFIC MANAGEMENT NETWORK SYSTEM 2009
2009/0132,648 CONTENT DELIVERY AND GLOBAL TRAFFIC MANAGEMENT NETWORK SYSTEM 2009
2009/0132,648 CONTENT DELIVERY AND GLOBAL TRAFFIC MANAGEMENT NETWORK SYSTEM 2009
2009/0132,648 CONTENT DELIVERY AND GLOBAL TRAFFIC MANAGEMENT NETWORK SYSTEM 2009

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