Importance

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Abstract

A data receiver circuit includes a transmission line to generate the appropriate timing for clock and data recovery. The transmission line receives a reference signal, and propagates the reference signal through at least two segments of predetermined lengths. The transmission line is configured with a first tab to extract, from the first predetermined length, a first delayed signal, and a second tab to extract, from the second predetermined length, a second delayed signal. A sampling circuit generates samples, at a first time period, from an input signal and the first delayed signal. The sampling circuit also generates samples, at a second time period, from the input signal and the second delayed signal. A capacitance control device to adjust the capacitance of the transmission line is disclosed. The data receiver circuit and the transmission line may be both fabricated on an integrated circuit, or the transmission line may be implemented external to the integrated circuit chip, such as on a package housing of the integrated circuit chip or on a printed circuit board for which the integrated circuit chip is mounted.

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First Claim