Method of depositing a uniform barrier layer and metal seed layer with reduced overhang over a plurality of recessed semiconductor features

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United States of America Patent

PATENT NO 8158511
APP PUB NO 20110256716A1
SERIAL NO

13068821

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Abstract

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A method of depositing a metal seed layer with underlying barrier layer on a wafer substrate comprising a plurality of recessed device features. A first portion of the barrier layer is deposited on the wafer substrate without excessive build-up of barrier layer material on the openings to the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. Subsequently, a metal seed layer is deposited using the same techniques used to deposit the barrier layer, to avoid excessive build up of metal seed layer material on the openings to the features, with minimal sputtering of the barrier layer surface.

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Patent Owner(s)

Patent OwnerAddress
APPLIED MATERIALS INC3050 BOWERS AVENUE SANTA CLARA CA 95054

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Fusen E Cupertino, US 54 947
Chiang, Tony Mountain View, US 137 4671
Chin, Barry L Saratoga, US 51 2796
Ding, Peijun San Jose, US 132 3424
Kohara, Gene Y Fremont, US 19 480
Xu, Zheng Foster City, US 334 5242
Yao, Gongda Fremont, US 37 832
Zhang, Hong Fremont, US 882 11808

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