Simplifying and speeding the management of intra-node cache coherence
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United States of America Patent
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Apr 17, 2012
Grant Date -
Mar 24, 2011
app pub date -
Nov 24, 2010
filing date -
Feb 24, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
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