Method and apparatus for implementing a task-based interface in a logic verification system

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8161502
APP PUB NO 20100083289A1
SERIAL NO

12239706

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

Method and apparatus for implementing a task-based interface in a logic verification system is described. In some examples, a task server and a context memory are implemented in a hardware accelerator for a task. The task server is configured for communication with the logic design. A task stub configured for execution by a computer for the task is generated. Calls to the task are received from a test bench in the computer at the task stub. Remote procedure call (RPC) channels are established in response to the calls. Values of input arguments for the calls are transferred to the context memory through the RPC channels. Execution of threads of the task in the task server is triggered using the values of the input arguments in the context memory as parametric input.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE SAN JOSE CA 95134

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Peng, Song San Jose, US 58 350
Shen, Quincy Saratoga, US 1 5
Tseng, Ping-sheng Saratoga, US 21 1821

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation