Semiconductor memory system and signal processing system
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United States of America Patent
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Apr 24, 2012
Grant Date -
May 15, 2008
app pub date -
Nov 21, 2007
filing date -
May 31, 2004
priority date (Note) -
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Abstract
A semiconductor memory device provided with a data input portion for receiving 1 page's worth of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words and transferring the same to a bank (A) or a bank (B), and a data output portion for receiving 1 page's worth of data including main code words transferred from the data latch circuit, correcting the error data when there is within a predetermined number of error data for each main code word, adding the error information for read each read code word except check code (parity data), and transferring the same to a host side, and a signal processing system using the same.
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