System and method for testing a memory
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United States of America Patent
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May 8, 2012
Grant Date -
Mar 3, 2005
app pub date -
Aug 29, 2003
filing date -
Aug 29, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
A computer system comprising a processor, a memory, and a memory controller coupled to the processor and the memory is provided. The memory controller comprises a first cache and a cache control. The cache control is configured to cause a portion of the memory to be copied into the first cache. The cache control is configured to cause first information to be provided from the first cache to the processor in response to receiving a read transaction from the processor that includes an address in the portion of memory during testing of the portion.
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