Packing two packed signed data in registers with saturation
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United States of America Patent
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May 29, 2012
Grant Date -
Sep 8, 2011
app pub date -
May 16, 2011
filing date -
Dec 2, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A processor comprising a register file, and a decoder to decode an instruction to specify a first source register having a first packed signed 16-bit integers, and to specify a second source register having a second packed signed 16-bit integers. A functional unit to generate a result to be stored in a specified destination. The result including a third packed 8-bit integers including an integer for each integer in the first packed integers, and an integer for each integer in the second packed integers. The integers corresponding to the first packed integers next to one another in the result. The integers corresponding to the second packed integers next to one another. A highest order integer of the result corresponding to a highest order integer of the first packed integers. A lowest order integer of the result corresponding to a lowest order integer of the second packed integers.
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