US Patent No: 8,193,051
Number of patents in Portfolio can not be more than 2000
Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics
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Jun 5, 2012
Issued date -
Mar 14, 2011
filing date -
13/047,172
serial no -
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Abstract
The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.
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First Claim
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 6,541,079 Engineered high dielectric constant oxide and oxynitride heterostructure gate dielectrics by an atomic beam deposition technique | 85 | 1999 | |
| 6,831,339 Aluminum nitride and aluminum oxide/aluminum nitride heterostructure gate dielectric stack based field effect transistors and method for forming same | 11 | 2001 | |
| 6,891,231 Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier | 6 | 2001 | |
| 6,846,734 Method and process to make multiple-threshold metal gates CMOS technology | 36 | 2002 | |
| 2005/0258,491 Threshold and flatband voltage stabilization layer for field effect transistors with high permittivity gate oxides | 8 | 2004 | |
| 7,271,455 Formation of fully silicided metal gate using dual self-aligned silicide process | 7 | 2004 | |
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| 5,763,922 CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers | 114 | 1997 | |
| 6,538,278 CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers | 30 | 2000 | |
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| 6,040,769 Detecting device and an alarm system | 13 | 1999 | |
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| 6,803,248 Chemistry for etching quaternary interface layers on InGaAsP mostly formed between GaAs and InxGa(1-x)P layers | 6 | 2001 | |
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| 2004/0185,624 Semiconductor device and method for fabricating the same | 4 | 2004 | |
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| 6,878,598 Method of forming thick metal silicide layer on gate electrode | 4 | 2003 | |
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| 5,668,028 Method of depositing thin nitride layer on gate oxide dielectric | 29 | 1995 | |
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| 6,407,435 Multilayer dielectric stack and method | 192 | 2000 | |
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| 2005/0079,695 Process for fabricating a transistor with a metal gate, and corresponding transistor | 7 | 2004 | |
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| 7,067,379 Silicide gate transistors and method of manufacture | 16 | 2004 | |
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