US Patent No: 8,193,062
Number of patents in Portfolio can not be more than 2000
Asymmetric silicon-on-insulator SRAM cell
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Jun 5, 2012
Issued date -
Sep 25, 2009
filing date -
12/566,717
serial no -
In Force
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Abstract
A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric.
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First Claim
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 2007/0211,519 MEMORY CELLS IN DOUBLE-GATE CMOS TECHNOLOGY PROVIDED WITH TRANSISTORS WITH TWO INDEPENDENT GATES | 7 | 2007 | |
| 2008/0175,039 Memory cell provided with dual-gate transistors, with independent asymmetric gates | 3 | 2007 | |
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| 6,466,489 Use of source/drain asymmetry MOSFET devices in dynamic and analog circuits | 31 | 2001 | |
| 2006/0274,569 Semiconductor device including back-gated transistors and method of fabricating the device | 25 | 2005 | |
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| 5,348,903 Process for fabricating a semiconductor memory cell having thin-film driver transistors overlapping dual wordlines | 28 | 1992 | |
| 5,363,328 Highly stable asymmetric SRAM cell | 10 | 1993 | |
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| 2006/0240,653 One-device non-volatile random access memory cell | 5 | 2006 | |
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| 5,354,703 EEPROM cell array with tight erase distribution | 8 | 1993 | |
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