US Patent No: 8,193,065
Number of patents in Portfolio can not be more than 2000
Asymmetric source and drain stressor regions
Stats
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Jun 5, 2012
Issued date -
May 3, 2011
filing date -
13/099,406
serial no -
In Force
status
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Abstract
A method forms a structure has a substrate having at least one semiconductor channel region, a gate dielectric on the upper surface of the substrate over the semiconductor channel region, and a gate conductor on the gate dielectric. Asymmetric sidewall spacers are located on the sidewalls of the gate conductor and asymmetric source and drain regions are located within the substrate adjacent the semiconductor channel region. One source/drain region is positioned closer to the midpoint of the gate conductor than is the other source/drain region. The source and drain regions comprise a material that induces physical stress upon the semiconductor channel region.
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First Claim
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 7,166,897 Method and apparatus for performance enhancement in an asymmetrical semiconductor device | 6 | 2004 | |
| 7,288,448 Method and apparatus for mobility enhancement in a semiconductor device | 12 | 2004 | |
| 7,105,395 Programming and erasing structure for an NVM cell | 2 | 2004 | |
| 7,195,983 Programming, erasing, and reading structure for an NVM cell | 2 | 2004 | |
| 2006/0170,016 Asymmetric spacers and asymmetric source/drain extension layers | 4 | 2005 | |
| 8,076,189 Method of forming a semiconductor device and semiconductor device | 8 | 2006 | |
| 8,039,341 Selective uniaxial stress modification for use with strained silicon on insulator integrated circuit | 1 | 2006 | |
| 7,572,706 Source/drain stressor and method therefor | 1 | 2007 | |
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| 6,815,317 Method to perform deep implants without scattering to adjacent areas | 8 | 2002 | |
| 2007/0235,802 Method to control source/drain stressor profiles for stress engineering | 17 | 2006 | |
| 2008/0006,818 STRUCTURE AND METHOD TO FORM MULTILAYER EMBEDDED STRESSORS | 20 | 2006 | |
| 2008/0233,691 METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS | 5 | 2007 | |
| 7,646,039 SOI field effect transistor having asymmetric junction leakage | 2 | 2007 | |
| 2009/0032,845 SOI FIELD EFFECT TRANSISTOR HAVING ASYMMETRIC JUNCTION LEAKAGE | 6 | 2007 | |
| 2009/0020,830 ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD | 2 | 2007 | |
| 2008/0185,662 STRUCTURE AND METHOD FOR FORMING ASYMMETRICAL OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS | 3 | 2008 | |
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| 6,916,716 Asymmetric halo implants | 6 | 2003 | |
| 7,144,782 Simplified masking for asymmetric halo | 3 | 2004 | |
| 7,354,839 Gate structure and a transistor having asymmetric spacer elements and methods of forming the same | 9 | 2005 | |
| 2006/0194,381 Gate structure and a transistor having asymmetric spacer elements and methods of forming the same | 3 | 2005 | |
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| 7,883,980 Insulated gate field effect transistor having passivated schottky barriers to the channel | 2 | 2006 | |
| 2007/0026,591 Insulated gate field effect transistor having passivated schottky barriers to the channel | 6 | 2006 | |
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| 2007/0132,038 Embedded stressor structure and process | 21 | 2005 | |
| 2007/0138,570 Formation of raised source/drain structures in NFET with embedded SiGe in PFET | 24 | 2005 | |
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| 2007/0057,287 Embedded SiGe stressor with tensile strain for NMOS current enhancement | 14 | 2005 | |
| 2007/0173,022 Defect-free SiGe source/drain formation by epitaxy-free process | 9 | 2006 | |
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| 2010/0025,744 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME | 1 | 2009 | |
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| 6,104,064 Asymmetrical transistor structure | 2 | 1999 | |
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| 2009/0032,841 Semiconductor Devices and Methods of Manufacture Thereof | 2 | 2007 | |
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| 7,888,221 Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions | 2 | 2008 | |
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| 2009/0011,569 ELECTRICAL DEVICE AND METHOD FOR FABRICATING THE SAME | 1 | 2008 | |
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| 2008/0290,422 ASYMMETRIC FIELD EFFECT TRANSISTORS (FETs) | 1 | 2008 | |
| 2008/0311,720 Short channel effect of MOS devices by retrograde well engineering using tilted dopant implantation into recessed source/drain regions | 1 | 2008 | |
Patent Citation Ranking
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