US Patent No: 8,193,065

Number of patents in Portfolio can not be more than 2000

Asymmetric source and drain stressor regions

ALSO PUBLISHED AS: 20110212587

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Abstract

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A method forms a structure has a substrate having at least one semiconductor channel region, a gate dielectric on the upper surface of the substrate over the semiconductor channel region, and a gate conductor on the gate dielectric. Asymmetric sidewall spacers are located on the sidewalls of the gate conductor and asymmetric source and drain regions are located within the substrate adjacent the semiconductor channel region. One source/drain region is positioned closer to the midpoint of the gate conductor than is the other source/drain region. The source and drain regions comprise a material that induces physical stress upon the semiconductor channel region.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
INTERNATIONAL BUSINESS MACHINES CORPORATIONARMONK, NY76218

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Johnson, Jeffrey B Essex Junction, VT 186 688
Ontalus, Viorel C - 36 23

Cited Art Landscape

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (8)
6,815,317 Method to perform deep implants without scattering to adjacent areas 12 2002
2007/0235,802 Method to control source/drain stressor profiles for stress engineering 26 2006
2008/0006,818 STRUCTURE AND METHOD TO FORM MULTILAYER EMBEDDED STRESSORS 24 2006
2008/0233,691 METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS 7 2007
7,646,039 SOI field effect transistor having asymmetric junction leakage 2 2007
2009/0032,845 SOI FIELD EFFECT TRANSISTOR HAVING ASYMMETRIC JUNCTION LEAKAGE 8 2007
2009/0020,830 ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 5 2007
2008/0185,662 STRUCTURE AND METHOD FOR FORMING ASYMMETRICAL OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS 5 2008
 
FREESCALE SEMICONDUCTOR, INC. (7)
7,166,897 Method and apparatus for performance enhancement in an asymmetrical semiconductor device 6 2004
7,288,448 Method and apparatus for mobility enhancement in a semiconductor device 12 2004
7,105,395 Programming and erasing structure for an NVM cell 2 2004
2006/0170,016 Asymmetric spacers and asymmetric source/drain extension layers 5 2005
8,076,189 Method of forming a semiconductor device and semiconductor device 22 2006
8,039,341 Selective uniaxial stress modification for use with strained silicon on insulator integrated circuit 3 2006
7,572,706 Source/drain stressor and method therefor 1 2007
 
ADVANCED MICRO DEVICES, INC. (4)
6,916,716 Asymmetric halo implants 9 2003
7,144,782 Simplified masking for asymmetric halo 6 2004
7,354,839 Gate structure and a transistor having asymmetric spacer elements and methods of forming the same 13 2005
2006/0194,381 Gate structure and a transistor having asymmetric spacer elements and methods of forming the same 4 2005
 
ACORN TECHNOLOGIES, INC. (2)
7,883,980 Insulated gate field effect transistor having passivated schottky barriers to the channel 6 2006
2007/0026,591 Insulated gate field effect transistor having passivated schottky barriers to the channel 8 2006
 
SAMSUNG ELECTRONICS CO., LTD. (2)
2007/0132,038 Embedded stressor structure and process 22 2005
2007/0138,570 Formation of raised source/drain structures in NFET with embedded SiGe in PFET 30 2005
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (2)
2007/0057,287 Embedded SiGe stressor with tensile strain for NMOS current enhancement 17 2005
2007/0173,022 Defect-free SiGe source/drain formation by epitaxy-free process 11 2006
 
FUJITSU SEMICONDUCTOR LIMITED (1)
2010/0025,744 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 1 2009
 
GLOBALFOUNDRIES INC. (1)
6,104,064 Asymmetrical transistor structure 2 1999
 
INFINEON TECHNOLOGIES AG (1)
2009/0032,841 Semiconductor Devices and Methods of Manufacture Thereof 5 2007
 
INTEL CORPORATION (1)
7,888,221 Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions 2 2008
 
NANYA TECHNOLOGY CORPORATION (1)
2009/0011,569 ELECTRICAL DEVICE AND METHOD FOR FABRICATING THE SAME 1 2008
 
PROGRESSIVE SEMICONDUCTOR SOLUTIONS LLC (1)
7,195,983 Programming, erasing, and reading structure for an NVM cell 7 2004
 
Other [Check patent profile for assignment information] (2)
2008/0290,422 ASYMMETRIC FIELD EFFECT TRANSISTORS (FETs) 2 2008
2008/0311,720 Short channel effect of MOS devices by retrograde well engineering using tilted dopant implantation into recessed source/drain regions 1 2008

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (1)
8,502,316 Self-aligned two-step STI formation through dummy poly removal 0 2010

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