I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures

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United States of America Patent

PATENT NO 8195856
SERIAL NO

12840742

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Abstract

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A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).

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Patent Owner(s)

  • PACT XPP TECHNOLOGIES AG

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Münch, Robert Karlsruhe, DE 10 153
Vorbach, Martin Karlsruhe, DE 174 5370

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