Memory controller, memory system with memory controller, and method of controlling flash memory

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United States of America Patent

PATENT NO 8200892
APP PUB NO 20100205357A1
SERIAL NO

12701831

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Abstract

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In the control of the number of program-erase cycles, when assigning a logical block (LB) to a physical block (PB), the number of program-erase cycles of a first PB and that of a second PB are compared, which first PB is a free PB of which the number of program-erase cycles is the smallest among that of free PBs, which second PB is a PB earliest assigned a LB among PBs each assigned a LB. As a result, in a case where the number of program-erase cycles of the first PB is larger by a predetermined value or more than that of the second PB, data stored in the second PB are transferred to a free PB of which the number of program-erase cycles is the largest among free PBs, and then the LB is assigned to the second PB.

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Patent Owner(s)

Patent OwnerAddress
TDK CORPORATIONTOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Mukaida, Naoki Tokyo, JP 15 615

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